Browsing by Author "Wang, Jen-Peng"

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A 3-GHz, 22-ps/dec Dynamic Comparator using Negative Resistance Combined with Input Pair
(2010-01-01)
Chen, Bo-Wei
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Wang, Jen-Peng
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Tsai, Chia-Ming
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A high speed, low delay/log(Delta Vin) dynamic comparator using negative resistance combined with input differential pair is proposed and designed in TSMC 90nm CMOS process technology. The delay/log(Delta Vin) of the comparator is 22ps/dec and consumes 213 mu W at 3GHz clock rate and 1.2V supply. The standard deviation of the comparator input refer offset is 25mV.