Browsing by Author "Wang, Jian-Hao"

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A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control
(2013-01-01)
Liao, Wei-Nan
;
Lien, Nan-Chun
;
Chang, Chi-Shin
;
Chu, Li-Wei
;
Yang, Hao-I
This paper presents a 40nm 1.0Mb pipeline 6T SRAM featuring digital-based Bit-Line Under-Drive (BLUD) with large-signal sensing and Three-Step-Up Word-Line (TSUWL) to improve RSNM, Read performance and Write-ability. An Adaptive DataAware Write-Assist (ADAWA) with VCS tracking is employed to further improve Write-ability while ensuring adequate stability for half-selected cells on the selected bit-lines. An Adaptive Voltage Detector (AVD) with binary boosting control is used to mitigate gate dielectric over-stress. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 1.07GHz@1.2V and 887MHz@1.1V at 25 degrees C. The measured power consumption is 43.47mW (Active)/3.91mW (Leakage) at 1.1V and 8.97mW (Active)/0.52mW (Leakage) at 0.7V, TT, 25 degrees C.
A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist
(2013)
Chang, Chi-Shin
;
Yang, Hao-I
;
Liao, Wei-Nan
;
Lin, Yi-Wei
;
Lien, Nan-Chun
We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of 800MHz@1.2V and 25 degrees C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25 degrees C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25 degrees C.
Impacts of Work Function Variation and Line Edge Roughness on Hybrid TFET-MOSFET Monolithic 3D SRAMs
(2017-01-01)
Wang, Jian-Hao
;
Su, Pin
;
Chuang, Ching-Te
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We analyze the variability of 7T hybrid TFET-MOSFET SRAM and 8T MOSFET SRAM in monolithic 3D technology operating at ultra-low voltage. The impacts of work function variation (WFV) and line edge roughness (LER) on SRAM cell stability, leakage power and performance are investigated and compared using 3D atomistic TCAD mixed-mode Monte-Carlo simulations. The results indicate that WFV and LER have different impacts on read disturb and V-write,V- 0, which dominate SRAM stability and is determined by the distinct current drive of TFET and MOSFET. The performance is influenced by the different variations of gate capacitance (C-g) under WFV and LER.