Browsing by Author "Wang, KB"

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A parallel algorithm for generating chain code of objects in binary images
(2003-02-01)
Chia, TL
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Wang, KB
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Chen, LR
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Chen, Z
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資訊科學與工程研究所
This paper addresses parallel execution of chain code generation on a linear array architecture. The contours in the proposed algorithm are viewed as a set of edges (or contour segments) that can be traced by a top-down contour tracing method to generate the chain codes for the outer and inner object contours. A parallel algorithm that contains the chain code generating rules and operations needed is also described, and the algorithm is mapped onto a one-dimensional systolic array containing [(1)/(2)(N + 1)] processing elements (PEs) to devise this architecture. The architecture extracts the contours of objects and quickly generates the corresponding chain codes after the image data in all rows are inputted in a linear fashion. The total processing time for generating the chain codes in an N x N image is O(3N). By doing so, the real-time requirement is fulfilled and its execution time is independent of the image content. In addition, a partition method is developed to process an image when the parallel architecture has a fixed number of PEs; say two or more. The total execution time for an N x N image by employing a fixed number of PEs is N(N + 1)/M + 2(M - 1), when M is the fixed number of PEs. (C) 2002 Elsevier Science Inc. All rights reserved.
Parallel distance transforms on a linear array architecture
(2002-04-30)
Chia, TL
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Wang, KB
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Chen, Z
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Lou, DC
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資訊科學與工程研究所
Distance transformation (DT) has been widely used for image matching and shape analysis. In this paper, a parallel algorithm for computing distance transformation is presented. First, it is shown that the algorithm has an execution time of 6N - 4 cycles, for an N x N image using a parallel architecture that requires [N/2] parallel processors. By doing so, the real time requirement is fulfilled and its execution time is independent of the image contents. In addition, a partition method is developed to process an image when the parallel architecture has a fixed number of processing elements (PEs); say two or more. The total execution time for an N x N image by employing a fixed number of PEs is 2[N-2/M + 2(M - 1)], when M is the fixed number of PEs. (C) 2002 Elsevier Science B.V. All rights reserved.
Parallel execution of a connected component labeling operation on a linear array architecture
(2003-03-01)
Wang, KB
;
Chia, TL
;
Chen, Z
;
Lou, DC
;
資訊科學與工程研究所
This work presents a novel parallel algorithm and architecture for finding connected components in an image. Simulation results indicate that the proposed algorithm has an execution time of N-2 +6N-4 cycles for an NxN image using an architecture containing 4 parallel processors. The proposed hardware can process a 128 x 128 image in 0.8574 ms and uses only 4 processors, compared to 0.85 ms and 128 processors for the work of Ranganathan et al. [14], and 94.6 ms and 16384 processors for the MPP [22]. Among the advantages of the novel architecture are modularity, expandability, regular data flow, and simple hardware. These properties are extremely desirable for VLSI implementations. Additionally, the execution time of the algorithm is independent of its image content; thus, it is quite flexible.