Browsing by Author "Wang, KC"

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A BNF-based automatic test program generator for compatible microprocessor verification
(2004-01-01)
Wu, LM
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Wang, KC
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Chiu, CY
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資訊工程學系
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Department of Computer Science
A novel Backus-Naur-form- (BNF-) based method to automatically generate test programs from simple to complex ones for advanced microprocessors is presented in this paper. We use X86 architecture to illustrate our design method. Our method is equally applicable to other processor architectures by redefining BNF production rules. Design issues for an automatic program generator (APG) are first outlined. We have resolved the design issues and implemented the APG by a top-down recursive descent parsing method which was originated from compiler design. Our APG can produce not only random test programs but also a sequence of instructions for a specific module to be tested by specifying a user menu-driven file. In addition, test programs generated by our APG have the features of no infinite loop, not entering illegal states, controllable data dependency, flexible program size, and data cache testable. Our method has been shown to be efficient and feasible for the development of an APG compared with other approaches. We have also developed a coverage tool to integrate with the APG. Experimental evaluation of the generated test programs indicates that our APG, with the guidance of the coverage tool, only needs to generate a small number of test programs to sustain high coverage.
A cost effective distributed location management strategy for wireless networks
(1999)
Wang, KC
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Huey, J
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資訊工程學系
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Department of Computer Science
The mobility feature of mobile stations (MSs) imposes a large burden on network traffic control as a result of location management. Design issues of location management include MS registration (updating) and call set-up (paging). Previous approaches introduced several network topologies for updating and paging procedures, but most of them focused on a single problem: either updating optimization or paging optimization. In this paper, we design and integrate two mechanisms, distributed temporary location caches (TLCs) and distributed home location registers (HLRs), to reduce database access delay and to decrease network signaling traffic in both updating and paging for low power, low tier micro cellular systems. By using TLCs, our approach can improve the performance of updating and paging in comparison with previous approaches. Experimental results based on our analytic model show that our location management procedures have lower HLR access rate, lower registration cost, and lower call set-up cost than other approaches.
A cost-effective forward recovery checkpointing scheme in multiprocessor systems
(2000-01-01)
Wang, KC
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Wang, CC
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資訊工程學系
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Department of Computer Science
This paper proposes a novel and cost-effective forward recovery checkpointing scheme fur multiprocessor systems with duplex modular redundancy. In our scheme, one processing module is selected to retry the questionable checkpoint, and the other processing module executes toward the next checkpoint ii a mismatched comparison between the two processing modules occurs at any checkpoint. Those schemes using a spare module to retry need much time to initiate the module, and the extra cost is high. Although the traditional rollback scheme retries the questionable checkpoint without any spare module, it has longer average completion time than our scheme for a job under any fault distribution. In our scheme, besides transient faults, permanent faults can be located as well. Experimental results based on our mathematical models demonstrate that, under burst errors, the average completion time of our scheme is reduced by 50% compared with that of the traditional rollback and is comparable with that of the scheme using a spare module to retry. In addition, our scheme has the least total execution time (the most cost-effectiveness) among the three schemes under any fault distribution.
A fair scheduling algorithm with adaptive compensation in wireless networks
(2001)
Wang, KC
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Chin, YL
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資訊工程學系
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Department of Computer Science
In this paper, we propose a fair scheduling algorithm with adaptive compensation (AC-FQ) for wireless networks, which can achieve fairness as well as graceful QoS degradation. AC-FQ changes a flow's weight according to its queue length. A flow with large (small) queue length means its traffic load is heavy (tight). In this way, AC-FQ can not only adaptively compensate recovered error-prone flows based on its traffic load, but also does not degrade the QoS of other error-free flows. Simulation results show that, without sacrificing throughput (queuing delay), ACFQ has less queuing delay (higher throughput) than CIF-Q, which also adopted a compensation mechanism for real-time (non-real-time) applications. Theoretical analysis of AC-FQ supports that our algorithm has bounds on fairness and throughput.
A hybrid overlay multicast routing protocol for mobile ad hoc networks
(2005)
Chen, CK
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Wang, KC
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Lee, LS
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資訊工程學系
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Department of Computer Science
We propose a novel multicast routing protocol, called Hybrid Overlay Multicast Routing Protocol (HOMRP) for MANETs (Mobile Ad hoc NETworks). Existing overlay and mesh multicast routing protocols in MANETs have the main drawback of low packet delivery ratio and high control overhead, respectively. In order to improve these shortcomings, we integrate multicasting and unicast tunnels for efficient packet delivery. In HOMRP, it creates multiple local multicast trees. Each pair of parent node and child node in a local multicast tree is at a distance of one-hop. It uses multicasting to deliver multicast packets in local multicast trees. This will provide efficient data forwarding. Unicast tunnels are used for transmitting packets between local multicast trees. Simulation results have shown that the packet delivery ratio of HOMRP is 50% better than that of AMRoute and is close to that of ODMRP. HOMRP reduces 18% control overhead compared to ODMRP and reduces 9% end-to-end packet delay compared to AMRoute.
An All-MPLS approach for UMTS 3G core networks
(2003)
Chueh, HS
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Wang, KC
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資訊工程學系
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Department of Computer Science
In this paper, we present an all-MPLS approach for UMTS 3G core networks. GTP-tunnel has been defined by 3GPP as the transport mechanism for UMTS. For each packet transmission, extra GTP, UDP, and IP headers (40-byte) are required. For short packets, such as VoIP payloads, transmission overhead is very high. Enhanced-GTP was proposed to eliminate the need for a GTP header. Since its operation mode is limited to non-transport mode only, NAT is required in GGSN. Furthermore, its performance improvement is limited, because an extra IP header (20-byte) is still needed. In response to these drawbacks, we propose to integrate MPLS technology to UNITS 3G core networks. We use MPLS-tunnel as the transport mechanism by using two-level MPLS labels (8-byte) to replace the GTP-tunnel. To the best of our knowledge, this is a novel approach, since no MPLS-based approach was ever proposed for UMTS 3G core networks. Our approach is feasible, since more and more routers are MPLS-capable. By reducing header overhead from 40-byte to 8-byte, our new approach improves transmission efficiency from 56.5% similar to 63% to 86.6% similar to 89.5% for VoIP payloads and also enhance packet forwarding efficiency. In addition, our all-MPLS approach offers better load balancing, better service resilience, and better QoS support, compared to existing approaches.
An efficient load balancing strategy for scalable WAP gateways
(2002)
Lin, TH
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Wang, KC
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資訊工程學系
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Department of Computer Science
In this paper we propose a load balancing strategy that has the following features: (1)estimating the potential load of real gateways with low computation and no communication overhead, (2) asynchronous alarm sent when the utilization of a real gateway exceeds a critical threshold, and (3) WAP-awareness. We also propose a scalable WAP gateway (SWG) that consists of a WAP dispatcher and a cluster of real gateways. The WAP dispatcher is a front-end distributor with our load balancing strategy. To prevent the WAP dispatcher from becoming a bottleneck, the WAP dispatcher distributes mobile clients' requests in kernel space and does not process outgoing gateway-to-client responses. Experimental results show that our SWG has better load balancing performance, throughput, and delay compared to the LVS and the Kannel gateway. Although WAP services are not so popular as expected, our load balancing strategy can be easily adapted to other distributed services.
An efficient load balancing strategy for scalable WAP gateways
(2005-06-02)
Lin, TH
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Wang, KC
;
Liu, AY
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資訊工程學系
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Department of Computer Science
Clustering provides a promising way to build a scalable, reliable, and high-performance WAP gateway architecture. However, this requires an efficient load balancing mechanism for assigning a request to a suitable gateway in the cluster, that can offer the best service. In addition, unpredictable connection time and nonuniformity of incoming load from different mobile clients are big obstacles to load balancing among real gateways. In this paper, we propose a load balancing strategy that has the following features: (1) estimating the potential load of real gateways with small computation time and no communication overhead, (2) asynchronous alarm sent when the utilization of a real gateway exceeds a critical threshold, and (3) WAP-awareness. We also propose a scalable WAP gateway (SWG) architecture that consists of a WAP dispatcher and a cluster of real gateways. The WAP dispatcher is a front-end distributor with our load balancing strategy. To prevent the WAP dispatcher from becoming a bottleneck, the WAP dispatcher distributes mobile clients' requests in kernel space and does not process outgoing gateway-to-client responses. Experiment results show that our SWG has better load balancing performance, throughput, and delay compared to the LVS and the Kannel gateway. (C) 2004 Elsevier B.V. All rights reserved.
An efficient probabilistic dynamic multicast routing in ATM networks
(1999-07-01)
Wang, KC
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Chen, JH
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資訊工程學系
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Department of Computer Science
In this paper, we propose a dynamic multicast routing algorithm based on probability for multimedia communications in an asynchronous transfer mode (ATM) network environment. For multimedia communications, we not only aim to arrange a transmission path with the minimal cost from a source node to each destination node, but also consider the dynamic multicast situation with node joining/leaving. To meet the above requirements, we develop a new method based on the relative probability of each node being truncated from the multicast connection tree, such that we can arrange a better path for a new joining node in such a way as to reduce the impact of leaving requests caused by other nodes in the multicast connection tree. The main contribution of this paper is a new and efficient dynamic multicast routing algorithm for multimedia communications which keeps the whole multicast connection tree near optimal in terms of cost inefficiency and guarantees that the transmission delay will be less than the preset bounded end-to-end delay. Simulation results show that under various sizes of networks and requests, the cost inefficiency of the multicast connection tree constructed by our approach is less than those of the trees constructed by the greedy algorithm and the weighted greedy algorithm, respectively.
An integrated multichannel selection and dynamic power control scheme for IEEE.802.11 wireless ad hoc networks
(2004)
Chung, J
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Wang, KC
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Shih, HC
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資訊工程學系
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Department of Computer Science
In this paper, we propose an efficient integrated scheme, E-MCPC, which combines multichannel selection with dynamic power control and is integrated into the IEEE 802.11 power saving mode. Most existing approaches adopted either multichannel selection or power control to improve throughput or to enhance power conservation in wireless ad hoc networks. These approaches only addressed one single issue, either reducing collisions but with inefficient power consumption or enhancing power conservation but with increased collisions. Simulation results have shown that our E-MCPC can achieve 1.2 times and 30% higher throughput, and 2.5 times and 2 times better power conservation compared to the IEEE 802.11 and MCPC, respectively, in a wireless ad hoc dense network with high traffic load.
Design and analysis of a growable multicast ATM switch
(2000-07-01)
Wang, KC
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Cheng, MH
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資訊工程學系
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Department of Computer Science
This work designs and analyzes a cost-effective growable multicast asynchronous transfer mode (ATM) switch that has a new grouping network structure. The proposed switch can easily be enlarged by using more stages, since both cell routing and contention resolution are designed to distribute ol er switch elements. Experimental results indicate that, by allowing valid cells to enter grouping networks from two directions (the west and north sides), the modular ATM sa itch proposed herein not only meets the ATM performance requirements for both unicasting and multicasting but also uses fen er switch elements and has a shorter cell delay than the ATM switch.
Design and analysis of QoS supported frequent handover schemes in microcellular ATM networks
(2001-07-01)
Wang, KC
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Lee, LS
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資訊工程學系
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Department of Computer Science
Wireless information networks need to employ small radio cells to support large user populations. However, this will impose extra burden, on network traffic control as a result of frequent handover behavior. Existing approaches to support a high handover rate still have cell loss and cell out-of-sequence penalty while the handover is in progress. This paper proposes a novel handover protocol that can avoid cell loss and guarantee cell sequence. It can enhance the performance of a microcellular asynchronous transfer mode network. By multicasting cells to a new base station before handover, our scheme can avoid cell loss and support a nonoverlapping microcell environment as well. The multicast of signaling messages during handover is to coordinate the cell transmission order between the old base station and the new base station to guarantee cell sequence. A formal representation of the handover protocol using finite-state diagrams has been developed to specify and verify the protocol. To guarantee quality of service, we present a hierarchical wireless call admission control to limit the number of in-progress connections and to prevent radio channel congestion. Mathematical models have been developed to analyze two quality-of-service, parameters: handover dropping probability and forced termination probability. Experimental results show that our hierarchical wireless call admission control can effectively lower the handover dropping probability and the forced termination probability in comparison with the single-layer wireless call admission control.
Design and implementation of a fault tolerant ATM switch
(1999-07-01)
Wang, KC
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Lin, FM
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資訊工程學系
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Department of Computer Science
In this paper, we propose a new method to build a fault tolerant ATM switch. Using this method, we can build an ATM switch which has two disjoint paths between each input/ output pair. The key component in the proposed switch is a 2 x 2 FTSE (Fault Tolerant Switching Element), which can be used as the basic building block for high speed ATM switches. The design of the FTSE-based fault tolerant ATM switch is based on a multi-path, self-routing principle. In terms of modularity, the proposed FTSE is suitable for building any multistage interconnection network (MINs). Thus, we can construct an MIN which has two levels of fault tolerance ability, and in which the redundant paths are in proportion to the network size. From the results of mathematical analysis, we conclude that our ATM switch uses fewer switching elements and has more redundant paths than other comparable ATM switches. The ATM switch is described using VHDL. By means of VHDL simulation, we verify the functionality of the switch. We have also synthesized the ATM switch to evaluate its delay and area. The experimental results demonstrate that the reliability/cost ratio of the fault tolerant FTSE-based ATM switch is better than those of other comparable switches.
Design and performance analysis of a growable multicast ATM switch
(1997)
Wang, KC
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Cheng, MR
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交大名義發表
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資訊工程學系
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National Chiao Tung University
In this paper, we design and analyze a growable multicast ATM switch. It can grow to a large size since both cell routing and contention resolution are designed to distribute over switch elements, and the switch structure is modular. The output ports are partitioned into groups to permit sharing of routing paths. The concept of group routing helps reduce an order of magnitude of switch elements. A two-stage switch architecture is described to illustrate our design principle. The switch can be easily expanded to a larger sire by using more stages. The performance analysis of the switch in terms of cell loss rate, cell delay, mean queue length, mean waiting time, and throughput is conducted using the M/Geom/1 model. Experimental results show that the proposed ATM switch not only meets the ATM performance requirements either for unicasting or multicasting but also uses fewer switch elements and has less delay than other comparable switches.
Effect of the transition metal on the synthesis of quaternary sulfides MPb8In17S34 (M = Cu, Ag, Au)
(2006-02-20)
Wang, KC
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Lee, CS
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應用化學系
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Department of Applied Chemistry
Quaternary sulfides MPb8In17S34 (M = Cu, Ag, Au) were synthesized at 1123 K from their elements in stoichiometric ratios. These compounds crystallize in monoclinic space group P2(1)/m. The crystal structures feature combinations of (2)(infinity)[InS2] (NaCl111-type) and (2)(infinity)[MPb2In3S6] (NaCl100-type) slabs. These compounds are semiconductors with band gaps near 1.3 eV.
Enhancing Bluetooth performance in interference environments via channel-state-dependent packet scheduling with adaptive packet selection
(2004)
Shih, CH
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Wang, KC
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Liu, AY
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資訊工程學系
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Department of Computer Science
In this paper, we propose a Bluetooth channel state dependent data segmentation and reassembly (CSD-SAR) scheme and a queue state dependent priority (QSD-PR) scheduling policy. The CSD-SAR maintains a receiving frequency table to predict channel conditions and selects the best packet type and packet size to transmit data. In addition, the QSD-PR also uses the receiving frequency table to avoid bad frequencies and gives a selected master-slave pair, which has more queued data to send between each other and has a higher priority to eliminate the wastage of slots. The conventional scheduling policy, Round Robin (RR), yields poor performance with the time division duplex (TDD) based MAC protocol and results in slot wastage and may not ensure fairness. Simulation results show that our proposed scheme achieves better link utilization and higher throughput with bounded delay compared to the RR scheme in error-free and error-prone environments. Our scheme can also eliminate interference to other wireless networks that share the same spectrum, such as WLANs, by avoiding selecting channels occupied by other networks.
Fault coverage estimation model for partially testable multichip modules
(1997)
Tseng, WD
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Wang, KC
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資訊工程學系
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Department of Computer Science
This paper proposes a simple and efficient model for designers to estimate fault coverage for partially testable MCMs. This model relates fault coverage, test methodology, and the ratio and distribution of DFT dies (dies with design for testability features) in an MCM. Experimental results show that our model can efficiently predict the fault coverage of a partially testable MCM with less than 5% deviation. In addition, the upper bound far fault coverage is also analyzed to guide the designers to know when to stop the effort in planning the use of DFT dies. Two defect level estimation models which relate fault coverage and manufacturing yield for measuring the test quality of MCMs under equiprobable and nonequiprobable faults, respectively, are also presented and evaluated.
Fuzzy-based circuit partitioning in built-in current testing
(1996)
Tseng, WD
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Wang, KC
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交大名義發表
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資訊工程學系
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National Chiao Tung University
Partitioning a digital circuit into modules before implementing on a single chip is key to balancing between test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistic analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible since IDDQ testing requires the measurement of an analog quantity rather than a digital signal. In this paper, we propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Evaluation results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning.
Fuzzy-based CMOS circuit partitioning in built-in current testing
(1999-03-01)
Tseng, WD
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Wang, KC
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資訊工程學系
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Department of Computer Science
We propose a fuzzy-based approach which pro,ides a soft threshold to determine the module size for CMOS circuit partitioning in built-in current testing (BICT). Experimental results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning in comparison with other approaches with a fixed threshold, and a better module size can thus he determined to reflect a change of circuit properties.
High-performance hydrogenated amorphous-Si TFT for AMLCD and AMOLED applications
(2005-10-01)
Chen, CW
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Chang, TC
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Liu, PT
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Lu, HY
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Wang, KC
A novel technology for manufacturing high-performance hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) is developed in this letter. In the bottom gate light-shield a-Si:H TFT structure, the side edge of a-Si:H island is capped with extra deposition of heavily phosphorous-doped a-Si layer. Such an ingenuity can effectively eliminate the leakage path between the parasitic contacts of source/drain metal and the sidewall of a-Si:H island edge. In addition, electrical performance of the novel a-Si:H TFT device exhibits superior effective carrier mobility as high as 1.05 cm(2)/Vs, due to the enormous improvement in parasitic resistance. The impressively high performance of the proposed a-Si:H TFT provides the potential to apply foractive matrix liquid crystal display and active matrix organic light-emitting diode technology.