Browsing by Author "Wang, Li-Rong"

Now showing 1 - 5 of 5

A Low-Power Level-Converting Double-Edge-Triggered Flip-Flop Design
(2013-10-01)
Wang, Li-Rong
;
Lo, Kai-Yu
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a new double-edge-triggered implicitly level-converting flip-flop, suitable for a low-power and low-voltage design. The design employs a sense amplifier architecture to reduce the delay and power consumption. Experimentally, when implemented with a 130-nm, single-V-t and 0.84 V V-DD process, it achieves 64% power-delay product (PDP) improvement, and moreover, 78% PDP improvement when implemented with a mixed-V-t technology, as compared to that of the classic double-edge-triggered flip-flop design.
A reconfigurable MAC architecture implemented with mixed-V(t) standard cell library
(2008)
Wang, Li-Rong
;
Chiu, Yi-Wei
;
Hu, Chia-Lin
;
Tu, Ming-Hsien
;
Jou, Shyh-Jye
In this paper, a 32-bit reconfigurable multiplication-accumulation architecture, which can execute flexibly one 32x32, two 16x16 or four 8x8 two's complement multiply-accumulation, is proposed and demonstrated. It is based on the modified Booth encoding scheme and designed with techniques of reducing sign-extension bits, removing one extra partial product row and adjusting the positions of hot signals but with elegant modifications. It is implemented with a 130nm mixed-V(t) CMOS standard cell library and shows saving of area and power consumption by approximately 16% and 14% respectively as compared to the previous design.
A well-structured modified Booth multiplier design
(2008)
Wang, Li-Rong
;
Jou, Shyh-Jye
;
Lee, Chung-Len
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper proposes a well-structured modified Booth encoding (MBE) multiplier architecture. The design adopts an improved Booth encoder and selector to achieve an extra-row-removal and a hybrid spare-tree approach to design two's complementation circuit to both reduce the area and improve the speed. Experimental results on a 32 bit multiplier show that it obtains area and power savings of 15.8% and 11.7% respectively over the classical design and of 7.5% and 5.5% respectively over the design of the best performance reported so far.
Mixed-Vth (MVT) CMOS circuit design for low power cell libraries
(2007)
Lin, Jiun-Yi
;
Wang, Li-Rong
;
Hu, Chia-Lmi
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
Mixed-Vth (MVT) technique has been proposed to resize the MOS size and then reduce dynamic power in logic gates by applying a low threshold voltage to transistors in some critical paths, while a standard threshold voltage is used in non-critical paths. This paper presents 130nm and 90nm low power cell libraries using MVT technique. The dynamic power consumption of the cells has been reduced around 5% to 30% and with the same timing specifications.
Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design
(2011-06-01)
Wang, Li-Rong
;
Tu, Ming-Hsien
;
Jou, Shyh-Jye
;
Lee, Chung-Len
;
電機工程學系
This paper presents a well-structured modified Booth encoding (MBE) multiplier which is applied in the design of a reconfigurable multiply-accumulator (MAC) core. The multiplier adopts an improved Booth encoder and selector to achieve an extra-row-removal and uses a hybrid approach in the two's complementation circuit to reduce the area and improve the speed. The multiplier is used to form a 32-bit reconfigurable MAC core which can be flexibly configured to execute one 32 x 32, two 16 x 16 or four 8 x 8 signed multiply-accumulation. Experimentally, when implemented with a 130 nm CMOS single-V(t) standard cell library, the multiplier achieved a 15.8% area saving and 11.7% power saving over the classical design, and the reconfigurable MAC achieved a 4.2% area and a 7.4% power saving over the MAC design published so far if implemented with a mixed-V(t) standard cell library.