Browsing by Author "Wang, MC"

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A method for fabricating a superior oxide/nitride/oxide gate stack
(2004)
Chang, TC
;
Yan, ST
;
Liu, PT
;
Wang, MC
;
Sze, SM
A superior oxide/nitride/oxide (ONO) gate stack was demonstrated. High density plasma chemical vapor deposition was used to deposit the silicon nitride layer instead of the conventional low-pressure chemical vapor deposition for silicon/oxide/nitride/oxide/silicon technology. The densified nitride layer was performed by high-temperature dry oxidation to form a thermally grown blocking oxide layer on the silicon nitride rather than a deposited oxide layer. The ONO gate stack shows large memory window, high breakdown voltage, and reliable endurance characteristics, which is a potential candidate for future nonvolatile memory technology. (C) 2004 The Electrochemical Society.
Auger recombination enhanced hot carrier degradation in nMOSFETs with positive substrate bias
(2000)
Chiang, LP
;
Tsai, CW
;
Wang, T
;
Liu, UC
;
Wang, MC
Enhanced hot carrier degradation is observed in DTMOS-like operation mode. This phenomenon is attributed to Auger recombination assisted hot electron process. Measured hot electron gate current and light emission spectrum in nMOSFETs provide evidence that the high-energy tail of channel electrons is increased by the application of a positive substrate bias. As opposed to conventional hot carrier degradation, the Auger enhanced degradation exhibits positive temperature dependence and is more significant at low drain bias.
Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS process
(2001)
Ker, MD
;
Lo, WY
;
Chen, TY
;
Tang, H
;
Chen, SS
An experimental extraction to find the area-efficient compact layout rules to prevent latchup in bulk CMOS IC's is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances. A new efficient latchup prevention design, by adding the additional internal guard rings between the I/O cells and the internal core circuits, has been successfully proven in a 0.25-mum shallow-trench-isolation (STI) silicided bulk CMOS process. Through detailed experimental verification including temperature effect, the proposed extraction method to define compact layout rules has been established to save the silicon area of CMOS IC's, but still to maintain high enough latchup immunity in bulk CMOS IC's.
Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technology
(2001)
Ker, MD
;
Hong, KK
;
Chen, TY
;
Tang, H
;
Huang, SC
Electrostatic discharge (ESD) robustness of CMOS devices with four different layout structures fabricated in a 0.15-mum partially-depleted silicon-on-insulator (SOI) salicide CMOS process are verified by ESD tester. The second breakdown current (It2) of fabricated CMOS devices is also measured by the transmission line pulse generator (TLPG). The dependences of ESD robustness on the layout parameters of CMOS devices in this SOI CMOS process have been investigated to find the optimum layout rules for on-chip ESD protection design. The effectiveness of ESD clamp circuits designed with the gate-driven and substrate-triggered techniques are also compared in this SOI CMOS process.
Novel diode structures and ESD protection circuits in a 1.8-V 0.15-mu m partially-depleted SOI salicided CMOS process
(2001)
Ker, MD
;
Hung, KK
;
Tang, HTH
;
Huang, SC
;
Chen, SS
Valence-band tunneling enhanced hot carrier degradation in ultra-thin oxide nMOSFETs
(2000)
Tsai, CW
;
Gu, SH
;
Chiang, LP
;
Wang, TH
;
Liu, YC
Enhanced hot carrier degradation with stress V-g in the valence-band tunneling regime is observed. This degradation is attributed to channel hole creation by valence-band electron tunneling. The created holes provide for Auger recombination with electrons in the channel and thus increase hot electron energy. The valence-band tunneling enhanced hot carrier degradation becomes more serious as gate oxide thickness is reduced. In ultra-thin gate oxide nMOSFETs, our result shows that the valence-band tunneling enhanced degradation, as opposed to max. Tb stress induced degradation, exhibits positive dependence on substrate bias. This phenomenon may cause a severe reliability issue in positively biased substrate or floating substrate devices.