Browsing by Author "Wang, MF"

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A model for photoresist-induced charging damage in ultra-thin gate oxides
(1997)
Lin, HC
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Chien, CH
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Wang, MF
;
Huang, TY
;
Chang, CY
The role of photoresist (PR) in affecting the gate oxide damage during plasma processing boas reexamined in this work. if was observed that, during the O-2 plasma ashing, more severe antenna effect may occur in devices with PR covering. A model is proposed to explain this phenomenon. This model considers the ability of plasma current injection through the substrate contacts, which are hindered by PR covering, to adjust the potential difference between gate electrode and substrate. We Sound that the presence of PR, antenna ratio, and gate-oxide thickness are all important parameters for charging damage effect.
A physical model for the hysteresis phenomenon of the ultrathin ZrO2 film
(2002-10-01)
Wang, JC
;
Chiao, SH
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Lee, CL
;
Lei, TF
;
Lin, YM
This work studies and presents an inner-interface trapping physical model for the ultra-thin (effective oxide thickness=15 Angstrom) zirconium oxide (ZrO2) film to explain its hysteresis phenomenon. The shift of the capacitance-voltage characteristics swept from accumulation to inversion and then swept back with light illumination is about 110 mV, which is larger than the shift without light illumination (similar to45 mV). The mobile ion effect is obviated using bias-temperature stress measurement. The proposed model successfully explains not only the phenomenon but also the thickness effect for the capacitance-voltage characteristics and the different turn-around voltages of the current density-voltage characteristics of the zirconium dielectrics. (C) 2002 American Institute of Physics.
Ambipolar Schottky barrier silicon-on-insulator metal-oxide-semiconductor transistors
(2003-02-01)
Lin, HC
;
Wang, MF
;
Lu, CY
;
Huang, TY
;
電子工程學系及電子研究所
A novel Schottky barrier silicon-on-insulator metal-oxide-semiconductor field-effect transistor featuring metallic source/drain and an electrical drain junction has been fabricated and characterized. The formation of electrical drain junction, or the field-induced drain (FID), is controlled by a metal field-plate overlying the passivation oxide. Excellent ambipolar operation is demonstrated on the device. Specifically, on/off current ratios up to 10(8) and 10(7) are observed for p- and n-channel operations, respectively. Meanwhile, the off-state leakage current shows very weak dependence on the voltage difference between the main-gate and the drain, highlighting the effectiveness of FID. Finally, negative differential conductance effect is observed for n-channel operation, which is identified as due to dynamic hot electron trapping during device characterization. (C) 2002 Elsevier Science Ltd. All rights reserved.
Application of field-induced source/drain Schottky metal-oxide-semiconductor to fin-like body field-effect transistor
(2002-06-01)
Lin, HC
;
Wang, MF
;
Hou, FJ
;
Liu, JT
;
Huang, TY
A novel Schottky barrier silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) device was proposed and demonstrated, The new device features a silicide source/drain and field-induced source/drain (S/D) extensions. Excellent ambipolar performance with a near-ideal sub-threshold slope (similar to 60 mV/decade) and high on-/off-state current ratio (comparable to or higher than 10(9)) is realized, for the first time, on a single device. These encouraging results suggest that the new device may be suitable for some niche applications requiring simple and low-temperature processing of complementary metal-oxide-semiconductor(CMOS)-like devices.
Characteristics of polysilicon oxides combining N2O nitridation and CMP processes
(2000-08-01)
Lei, TF
;
Chen, JH
;
Wang, MF
;
Chao, TS
;
電子工程學系及電子研究所
This paper present a high-quality polysilicon oxide combining N2O nitridation and chemical mechanical polishing (CMP) processes. Experimental results indicate that polyoxide grown on the CMP sample exhibits a lower leakage current, higher dielectric breakdown field, higher electron barrier height, less electron trapping rate, higher charge-to-breakdown (Q(bd)), and lower density of trapping charge than those of non-CMP samples. In addition, the CMP process enhances nitrogen incorporation at the interface by the N2O nitridation, ultimately improving the polyoxide quality, Moreover, the CMP process smooths the surface of polysilicon and this planar surface reduces the out-diffusion of the phosphorous during thermal oxidation.
Effects of base oxide in HfSiO/SiO2 high-k gate stacks
(2004)
Wu, WH
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Chen, MC
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Wang, MF
;
Hou, TH
;
Yao, LG
Electrical characteristics of HfSiO/SiO2 high-k gate stacks have been extensively explored with regard to the effects of base oxide. The flatband voltage shift in N/PMOS capacitors is independent of base oxide thickness, and the dielectric breakdown of the gate stacks is determined by base oxide. In addition, base oxide thickness has a great impact on device performance and charge trapping, presumably due to remote Coulomb scattering (RCS) in the HfSiO bulk layer and direct tunneling through the base oxide. Threshold voltage instability induced by charge trapping will be a major reliability concern for Hf-based high-k gate dielectrics in the future.
Effects of N2O-annealed sacrificial oxide on the short-channel effects of nMOSFETs
(1998-02-19)
Jong, FC
;
Huang, TY
;
Chao, TS
;
Lin, HC
;
Wang, MF
The authors report the effects of N2O-annealed sacrificial oxide on nMOSFETs. It is demonstrated that by adding an N2O-annealing step to the sacrificial. oxide which was stripped off before growing the final gate oxide, the reverse short-channel effects (RSCE) can still be effectively suppressed.
Enhanced negative-bias-temperature instability of P-channel metal-oxide-semiconductor transistors due to plasma charging damage
(2002-04-01)
Lee, DY
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Lin, HC
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Wang, MF
;
Tsai, MY
;
Huang, TY
The effects of plasma charging on the negative-bias-temperature instability (NBTI) of p-channel metal-oxide-semiconductor (PMOS) transistors were explored in this work. It is clearly shown that the threshold voltage shift during bias-temperature stressing (BTS) could be enhanced by plasma charging damage. More importantly, we also found that electron trappings are aggravated by plasma charging, even on new devices with large antenna area ratios prior to BTS. Our charge pumping current measurements confirm that the interface-state density is increased for devices with large antennas, both before and after the BTS. This indicates, without ambiguity, that electron trapping is solely responsible for the observed low (in absolute value) threshold voltage in new devices with large antennas. Finally, it is proposed that the NBTI characterization can be used as a sensitive method for characterizing the antenna effects in devices with ultrathin gate oxide, which is particularly attractive in light of the fact that conventional indicators are becoming inadequate as oxide is scaled down.
Enhancement of integrity of polysilicon oxide by using a combination of N2O nitridation and CMP process
(1999-05-01)
Lei, TF
;
Chen, JH
;
Wang, MF
;
Chao, TS
;
電子工程學系及電子研究所
This work prepares and demonstrates, for the first time, a high-quality polysilicon oxide, by combining N2O nitridation and Chemical Mechanical Polishing (CMP) process. Our results demonstrate that capacitors with this process have an improved Q(bd) (charge-to-breakdown) due to the planar surface and more concentrated nitrogen at the interface of polysilicon oxide.
Evaluation of plasma charging damage in ultrathin gate oxides
(1998-03-01)
Lin, HC
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Chen, CC
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Chien, CH
;
Hsein, SK
;
Wang, MF
Monitoring of plasma charging damage in ultrathin oxides (e.g., <4 nm) is essential to understand its impact on device reliability. However, it is observed that the shift of several device parameters, including threshold voltage, transconductance, and subthreshold swing, are not sensitive to plasma charging and thus not suitable for this purpose. Consequently, some destructive methods, such as the charge-to-breakdown measurement, are necessary to evaluate plasma damage in the ultrathin oxides.
High-performance P-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions
(2003-02-01)
Lin, HC
;
Wang, MF
;
Hou, FJ
;
Lin, HN
;
Lu, CY
A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in, the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by, the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.
Impact of thermal stability on the characteristics of complementary metal oxide semiconductor transistors with TiN metal gate
(2002-02-01)
Wang, MF
;
Huang, TY
;
Kao, YC
;
Lin, HC
;
Chang, CY
The effects of rapid thermal annealing (RTA) performed after source/drain (S/D) implantation on the characteristics of complementary metal-oxide-semiconductor (CMOS) transistors with a TiN metal gate were investigated thoroughly. It was shown that n-channel devices require a higher thermal budget in order to reduce junction leakage, compared to p-channel devices. It was also found that the flat-band voltage and oxide thickness are both affected by the annealing temperature, particularly for p-channel devices. In n-channel devices, the gate leakage current level is highly dependent on channel length and RTA temperatures. Further analysis indicated that the agglomeration phenomenon during the high-temperature RTA step occurs more easily as the metal gate length becomes narrower. When this happens, gate oxide integrity is degraded, resulting in an increased gate leakage of n-channel transistors.
Oxide thickness dependence of plasma charging damage
(1999-03-01)
Lin, HC
;
Chen, CC
;
Wang, MF
;
Hsien, SK
;
Chien, CH
Charging damage induced in oxides with thickness ranging from 8.7 to 2.5 nm is investigated. Results of charge-to-breakdown (Q(bd)) measurements performed on control devices indicate that the polarity dependence increases with decreasing oxide thickness at both room and elevated temperature (180 degrees C) conditions. As the oxide thickness is thinned down below 3nm, the Q(bd) becomes very sensitive to the stressing current density and temperature. Experimental results show that severe antenna effect would occur during plasma ashing treatment in devices with gate oxides as thin as 2.6 nm. It is concluded that high stressing current level, negative plasma charging, and high process temperature are key factors responsible for the damage. (C) 1999 Elsevier Science Ltd. All rights reserved.
Simultaneous etching of polysilicon materials with different doping types by low-damage transformer-coupled plasma technique
(2002-09-01)
Hung, CC
;
Lin, HC
;
Wang, MF
;
Huang, TY
;
Shih, HC
The feasibility of simultaneously etching n(+), p(+), and undoped polysilicon (poly-Si) materials by a commercial transformer coupled plasma (TCP) reactor has been investigated in this study. Response surface methodology (RSM) was used to optimize process parameters including pressure, TCP source power, bias power, and Cl-2/HBr flow on the main etch step. Quantitative relationships between etching performance and process parameters were established. Our results indicate that there exists a process parameter window that meets the requirements of etching polysilicon with different doping types simultaneously. High etch rate, superior uniformity, good end point detection (EPD) characteristics and profile control can be simultaneously obtained with the optimized recipe, irrespective of the doping types. Furthermore, only minor plasma-induced damage is detected as monitored from antenna transistors' charge-to-breakdown (Q(bd)), threshold voltage and charge pumping current. (C) 2002 Elsevier Science B.V. All rights reserved.
The effects of shallow germanium halo doping on N-channel metal oxide semiconductor field effect transistors
(1999-01-15)
Wang, MF
;
Chien, CH
;
Chao, TS
;
Lin, HC
;
Jong, FC
In this paper, we report the use of shallow germanium halo doping on improving the short-channel effects of deep submicron n-channel metal-oxide-semiconductor field effect transistors. It is demonstrated that by adding a shallow (i.e., 10 keV) germanium large-angle-tilt implant (LATID), V-th lowering in short-channel transistors is significantly improved. The improvement is found to increase with increasing germanium dose. A low germanium dose (e.g., 5 x 10(12) cm(-2)) is also found to effectively improve the drain-induced barrier lowering (DIBL) of the short-channel transistors. Our results also show that junction leakage degradation, which has been previously reported to accompany germanium implants using higher energy, can be minimized by the shallow low-dose implant used in this study.
Thermal stability of PVD TiN gate and its impacts on characteristics of CMOS transistors
(2001)
Wang, MF
;
Kao, YC
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Huang, TY
;
Lin, HC
;
Chang, CY
The effects of rapid-thermal annealing (RTA) after source/drain (S/D) implant on the characteristics of CMOS transistors with sputtered TiN gate were investigated. Our results indicate that n(+)/p junctions need higher thermal budget than p(+)/n junctions to achieve low leakage performance. It was also found fron C-V measurements that the flat-band voltage and oxide thickness are both affected by the annealing treatment, especially for p-channel devices. A hump in the subthreshold characteristics of p-channel transistors is observed, owing to the existence of a leakage path along the isolation edge. It is also shown that agglomeration phenomenon is easier to incur during the high-temperature RTA step as the metal gate width becomes narrower. When this happens, gate oxide integrity would be degraded, resulting in increased gate leakage of n-channel transistors.