Browsing by Author "Wang, Pei-Yu"

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A Novel Approach Using Discrete Grain-Boundary Traps to Study the Variability of 3-D Vertical-Gate NAND Flash Memory Cells
(2015-08-01)
Wang, Pei-Yu
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The 3-D NAND flash memory architectures will be a future trend, because they provide high memory capacity without aggressively scaling down. A vertical-gate (VG) structure composed of polysilicon (poly-Si) channels is a promising 3-D structure that could facilitate realizing an extremely tight-pitch NAND flash memory cell with high memory capacity. However, the variability of the VG memory cell induced by grain boundaries in the poly-Si channels is a major concern for aggressively scaled-down memory cells. In this paper, a discrete-trap approach is applied to emulate the real trap effects in a 3-D memory cell, and the 3-D structure geometry effects and the variation in the threshold voltage (V-T) induced by the discrete grain-boundary traps are studied. Various Delta V-T behaviors related to the structure geometry and trap position are examined. The effect of varying the body thickness on the Delta V-T is stronger than that of varying the channel width. This paper presents various cases for using the discrete-trap approach to study the variability of V-T in 3-D VG memory cells.
Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure
(2016-01-01)
Wang, Pei-Yu
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Tunnel field-effect transistor (FET) is a promising candidate in ultralow-power applications due to its distinct operation mechanism, namely band-to-band tunneling (BTBT). The integration of different low-bandgap materials is explored extensively to improve the ON-state BTBT current of the tunnel FETs. The epitaxial tunnel layer (ETL) tunnel FET integrated with the hetero-material system is a promising structure due to its process compatibility with CMOS technologies. In the scenario of n-channel operation, the concept of the suppression of the low electric field BTBT is proposed. The SiGe/Si hetero-material system is applied to the n-channel ETL tunnel FET to suppress the low electric field BTBT by the ETL band engineering. The optimized ETL tunnel FET exhibits a high ON-state BTBT current due to the low bandgap material in the ETL. The average SS behavior is also further improved by suppressing the low electric field BTBT. In this study, the design concept and the device parameters of the n-channel ETL tunnel FET are discussed in detail. The performances of the complementary ETL tunnel FETs using the SiGe/Si hetero-material system are also provided to enrich the value of the ETL tunnel FET in the circuit applications.
Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure
(2016-01)
Wang, Pei-Yu
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Tunnel field-effect transistor (FET) is a promising candidate in ultralow-power applications due to its distinct operation mechanism, namely band-to-band tunneling (BTBT). The integration of different low-bandgap materials is explored extensively to improve the ON-state BTBT current of the tunnel FETs. The epitaxial tunnel layer (ETL) tunnel FET integrated with the hetero-material system is a promising structure due to its process compatibility with CMOS technologies. In the scenario of n-channel operation, the concept of the suppression of the low electric field BTBT is proposed. The SiGe/Si hetero-material system is applied to the n-channel ETL tunnel FET to suppress the low electric field BTBT by the ETL band engineering. The optimized ETL tunnel FET exhibits a high ON-state BTBT current due to the low bandgap material in the ETL. The average SS behavior is also further improved by suppressing the low electric field BTBT. In this study, the design concept and the device parameters of the n-channel ETL tunnel FET are discussed in detail. The performances of the complementary ETL tunnel FETs using the SiGe/Si hetero-material system are also provided to enrich the value of the ETL tunnel FET in the circuit applications.
Enhancing the Performance of Germanium Channel nMOSFET Using Phosphorus Dopant Segregation
(2014-01-01)
Chen, Che-Wei
;
Tzeng, Ju-Yuan
;
Chung, Cheng-Ting
;
Chien, Hung-Pin
;
Chien, Chao-Hsin
In this letter, we present a high performance Ge n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a NiGe Schottky junction source/drain fabricated using phosphorus dopant segregation. Phosphorus atoms were implanted into NiGe and then driven toward the NiGe/p-Ge interface to depin the Fermi level and form a Schottky junction. A high effective barrier height (Phi(Bp)) of 0.57 eV, resulting in a high junction current ratio of >10(4) at the applied voltage vertical bar V-a vertical bar = +/- 1 V. The nMOSFET exhibited a high I-ON/I-OFF ratio of similar to 8 x 10(3) (I-D), similar to 10(5) (I-S), and a subthreshold swing of 138 mV/decade. The nMOSFET developed in this letter exhibited greater transconductance and a drain leakage current that is more than two orders of magnitude lower compared with nMOSFETs with the conventional n(+)/p junction.
Evaluation of Electrical Performance of Various Tunnel TFETs
(2015)
Huang, Chi
;
Hung, Tao-Yi
;
Wang, Pei-Yu
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
Tunnel field-effect transistor (TFET) is a promising device which has extraordinary performance on subthreshold swing and is feasible for ultralow power applications. However, one of the main factors of power dissipation and circuit delay among different designs of TFET, namely, parasitic capacitances, has not been discussed in detail. In this paper, parasitic capacitance of various types of TFETs are simulate and analyze.
Experimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF Ratio
(2015-12-01)
Wang, Pei-Yu
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A CMOS process compatible p-channel tunnel field-effect transistor (TFET) with an epitaxial tunnel layer (ETL) structure is demonstrated experimentally. The fabricated ETL p-TFET exhibits high tunneling current (I-ON similar to 0.17 mu A/mu m at vertical bar V-G vertical bar = 0.5 V after V-TH adjustment), ultra-low OFF-state current, and good average subthreshold swing (S.S. similar to 100 mV/decade up to 10 nA/mu m). Overall performance exceeds that of the current state-of-the-art Ge-based planar p-TFETs.
Investigation Into Gate-to-Source Capacitance Induced by Highly Efficient Band-to-Band Tunneling in p-Channel Ge Epitaxial Tunnel Layer Tunnel FET
(2016-04)
Wang, Pei-Yu
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The gate-to-source capacitance (C-GS) in the p-channel tunnel FET (pTFET) with a Ge epitaxial tunnel layer (ETL) structure is investigated. The characteristic of C-GS is revealed and studied with various frequencies and temperatures. Due to the highly efficient band-to-band tunneling (BTBT) in the Ge ETL pTFET, the minority carriers for the source can be generated by the BTBT process and can respond with the gate voltage. Therefore, the contribution of C-GS to the total gate capacitance in the ON-state would increase, which results in a decrease of the gate-to-drain capacitance. This property is beneficial to the suppression of the Miller capacitance effect on the TFET-based circuit.
Multi-gate non-volatile memories with nanowires as charge storage material
(2010-05-01)
Tsui, Bing-Yue
;
Wang, Pei-Yu
;
Chen, Ting-Yeh
;
Cheng, Jung-Chien
;
電子工程學系及電子研究所
Multi-gate non-volatile memory (NVM) cell is a promising approach in the next generation. In this work, the performance of NVMs using nanocrystals (NCs) and nanowires (NWs) as charge trapping materials were evaluated by three-dimensional simulation. It is found that the NWs located at different positions have different charge injection speeds. And the NW density will strongly affect the charge injection efficiency. The NW at channel center can result in large memory window and acceptable channel controllability. Although the total charges injected into NWs is lower than that injected into NCs under the same programming condition, using NWs as charge trapping material exhibits larger memory window and better channel controllability. It is suggested that the NW is a better choice than NC to be charge storage material from the perspective of memory performance. (C) 2010 Elsevier Ltd. All rights reserved.
Simulation of Grain-Boundary Traps Effect for 3D Vertical Gate NAND Flash Memory Cell : From Structure Geometry to Trap Description
(2014)
Wang, Pei-Yu
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
3D NAND Flash is the most promising memory architecture which can increase capacity continuously without aggressive scaling-down. The performance variability of the memory cell induced by the grain boundaries (GBs) of the poly-Si channel is a major concern. In this work, a full 3D simulation is performed to study the threshold voltage variability. The impact of the 3D structure geometry on the variation induced by the GB traps is discussed. In addition, a discrete-trap approach is also proposed to reflect the true behavior of the GB traps. A smaller variation in the discrete-trap approach is observed due to the local trap effect.
SixGe1-x Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET Improvement
(2013-12-01)
Wang, Pei-Yu
;
Tsui, Bing-Yue
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The tunnel field-effect transistor (FET) is a promising candidate for use in ultralow-power applications because of its distinct operation principle, namely, band to band tunneling (BTBT). However, the ON-state current of the tunnel device is extremely low because of the poor tunneling efficiency of the BTBT. In this paper, a novel epitaxial tunnel layer (ETL) structure combining vertical tunneling orientation was proposed. The ETL structure performs more favorably than does the traditional lateral tunnel FET structure in an all-silicon device. By using low bandgap materials in the ETL, the ON-state BTBT current increases and an extremely low intrinsic OFF-state current is maintained because of the small low bandgap junction area. The onset voltage of the bipolar BTBT can also be postponed using ETL band engineering. The optimized parameters of the SixGe1-x ETL tunnel FET structure increase the ON-state current 10(7)-10(8) times compared with that of the traditional lateral silicon tunnel FET. The minimal subthreshold swing (SS) and ON/OFF current ratio also improve, the SS decreases from 47 mV/decade to 29 mV/decade, and the ON/OFF current ratio increase from 10(5) to 10(10). In this paper, the effects of the ETL parameters on device performance are discussed in detail.