Browsing by Author "Wang, Po-Hao"

Now showing 1 - 7 of 7

A 0.48V 0.57nJ/Pixel Video-Recording SoC in 65nm CMOS
(2013-01-01)
Lin, Tay-Jyi
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Chien, Cheng-An
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Chang, Pei-Yao
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Chen, Ching-Wen
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Wang, Po-Hao
Adaptive Variable-Latency Cache Management for Low-Voltage Caches
(2014-01-01)
Yu, Yung-Hui
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Wang, Po-Hao
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Chen, Tien-Fu
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Lin, Tay-Jyi
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Wang, Jinn-Shyan
Scaling down the supply voltage for embedded SoC becomes a necessary technique to lower power requirements in mobile devices. However, caches become susceptible or even fail in low voltages, and distribution of access latencies is significantly increased in new technology nodes. Past researches suggested several solutions to deal with the memory reliability at low voltages, where a timing table records cache lines with latency faults. This paper proposes cache management strategies for variable-latency caches at low voltages. We analyze the locality effect and propose two methods to dynamically adapt latency faults at run time and give the advantages of those methods compared to traditional LRU for low-voltage caches.
Cross-matching caches: Dynamic timing calibration and bit-level timing-failure mask caches to reduce timing discrepancies with low voltage processors
(2016-06)
Wang, Po-Hao
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Tsai, Shang-Jen
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Tanjung, Rizal
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Lin, Tay-Jyi
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Wang, Jinn-Shyan
Voltage scaling is an effective technique to reduce power consumption in processor systems. Unfortunately, timing discrepancies between L1 caches and cores occur with the scaling down of voltage. These discrepancies are primarily caused by the severe process variations of a few slow SRAM cells. Most previous designs tolerated slow cells by adjusting access latency based on a coarse-grained track of cache blocks. However, these methods become insufficient when the amount of slow cells increases. This paper addresses the issue for an 8T SRAM cache and proposes a cross-matching cache that includes dynamic timing calibration and actual bit-level timing-failure toleration. (C) 2016 Elsevier B.V. All rights reserved.
Cylindrical Liquid Crystal Lenses System for Autostereoscopic 2D/3D Display
(2012)
Chen, Chih-Wei
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Huang, Yi-Pai
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Chang, Yu-Cheng
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Wang, Po-Hao
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Chen, Po-Chuan
The liquid crystal lenses system, which could be electrically controlled easily for autostereoscopic 2D/3D switchable display was proposed. The High-Resistance liquid crystal (HRLC) lens utilized less controlled electrodes and coated a high-resistance layer between the controlled-electrodes was proposed and was used in this paper. Compare with the traditional LC lens, the HR-LC Lens could provide smooth electric-potential distribution within the LC layer under driving status. Hence, the proposed HR-LC Lens had less circuit complexity, low driving voltage, and good optical performance also could be obtained. In addition, combining with the proposed driving method called dual-directional overdriving method, the above method could reduce the switching time by applying large voltage onto cell. Consequently, the total switching time could be further reduced to around 2second. It is believed that the LC lens system has high potential in the future.
ULV-Turbo Cache for an Instantaneous Performance Boost on Asymmetric Architectures
(2017-12-01)
Wang, Po-Hao
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Chien, Yung-Chen
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Tsai, Shang-Jen
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Lin, Xuan-Yu
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Tanjung, Rizal
An asymmetric architecture is commonly used in modern embedded systems to reduce energy consumption. The systems tend to execute more applications in the energy-efficient core, which typically employs ultralow voltage (ULV) to save energy. However, caches become a reliability and performance barrier that limits the minimum operating voltage and blocks system performance in the ULV environment. The poor performance of an ultralow-voltage core causes most workload requirements to awaken and then execute on the host core, leading to high energy consumption. In this paper, we propose a ULV-Turbo cache based on a ULV-selective-ally 8T static random access memory (SRAM) that is able to perform reliable ultralow-voltage operation and provide the speedup function of SRAM rows ally. The system is able to speed up the ULV core instantaneously and execute more applications with the ULV-Turbo cache. In our system-wide evaluation based on a real attitude and heading reference system workload on an asymmetric wearable system, the ULV-Turbo cache reduces the energy consumption of the entire system by approximately 36%.
Variation-Aware and Adaptive-Latency Accesses for Reliable Low Voltage Caches
(2013)
Wang, Po-Hao
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Cheng, Wei-Chung
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Yu, Yung-Hui
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Kao, Tang-Chieh
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Tsai, Chi-Lun
Contemporary cache is known for consuming a large part of total power in microprocessors. Voltage scaling had been used to reduce the power consumption of the cache. However, due to the impact of variations, SRAM cells of the cache could potentially fail when voltage dropping. To against variations, we need to increase the supply voltage for the safety margin, thus the cache costs large energy consumption. For eliminating the voltage safety margin, some prior works for SRAM failure tolerance designs were proposed. These schemes will result in worse energy consumption and cannot deal with dynamic variations. They still have a safety margin to resist dynamic variations. With the supply voltage scaling down, we find out that the major reason of failures is that some slow cells have longer latency. We call these cell faults as "latency fault". If each cache line can be accessed in an appropriate access time, the slower cells could be reused but not disable them. We propose a VAL-Cache adapting the access time to tolerate latency faults and which is able to scale down the voltage. And we also propose the latency-fault detector to detect latency faults at run-time so as to tolerate both static and dynamic variations. Our experimental results on Mibench and 0xbench benchmarks demonstrate that the energy consumption can be reduced 10%similar to 18% in average at a cost of acceptable performance loss.
Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations
(2016-10)
Wang, Po-Hao
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Cheng, Wei-Chung
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Yu, Yung-Hui
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Kao, Tang-Chieh
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Tsai, Chi-Lun
In modern embedded processor systems, energy efficiency is a critical issue. Unfortunately, to avoid cache memory (SRAM) faults from dynamic variations, caches generally operate at an elevated voltage to build a safety guardband that decreases energy efficiency. To address this issue, tolerating SRAM faults to eliminate the safety of a guardband without frequency scaling may be a viable solution. This study investigates the characteristics of low-voltage 8 T SRAM faults and demonstrates that most SRAM faults are typically caused by insufficient access times with variation effects and significantly reduced voltages. Thus, we propose an access-time fault-tolerant cache design based on a type of 8 T SRAM known as zero-counting and adaptive-latency cache (ZCAL cache), which can tolerate numerous access-time faults. ZCAL caches detect access-time faults dynamically using a lightweight error detection code ("0" counting) because access-time faults occur only when reading "0" bits on the 8 T SRAM; the cache then adapts its access time to tolerate the access-time faults with new cache management processes. With the ZCAL cache, the experimental results from the MiBench benchmarks indicate that the energy efficiency is improved by 17% on average and that the energy consumption is reduced by 22% from 0.76 to 0.63 V.