Browsing by Author "Wang, S. J."

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A Low Operating Voltage ZnO Thin Film Transistor Using a High-kappa HfLaO Gate Dielectric
(2010)
Su, N. C.
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Wang, S. J.
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Chin, Albert
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This study demonstrates the feasibility of producing a ZnO thin film transistor (TFT) using hafnium-lanthanum-oxide (HfLaO) as the gate dielectric. By integrating high-kappa HfLaO with an amorphous ZnO channel, the resulting HfLaO/ZnO TFTs display a low threshold voltage (V(T)) of 0.28 V, a small subthreshold swing (SS) of 0.26 V/dec, an acceptable mobility (mu(sat)) of 3.5 cm(2)/V s, and a good I(on)/I(off) ratio of 1 X 10(6). The SS heavily depends on the HfLaO/ZnO interface charges, a property which is related to the degree of crystallization of ZnO. The low VT and the small SS allow device voltage operation below 2 V for low power application. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3257607] All rights reserved.
Characteristics of Zinc Oxide Thin Film Transistors Fabricated by Location-Controlled Hydrothermal Method
(2010)
Yang, P. Y.
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Wang, J. L.
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Tsai, W. C.
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Wang, S. J.
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Chen, P. C.
In this paper, high-performance Zinc oxide (ZnO) thin-film transistors (TFTs) with bottom-gate (BG) structure and artificially location-controlled lateral grain growth have been prepared by low-temperature hydrothermal method. As the proper design of source/drain structure of ZnO/Ti/Pt thin films, the lateral grain growth can be artificially controlled in the desired location and the vertical grain boundary perpendicular to the current flow in the channel region can be reduced to single one. As compared with the conventional sputtered ZnO BG-TFTs, the proposed location-controlled hydrothermal ZnO BG-TFTs (W/L = 250 mu m/10 mu m) demonstrated the higher field-effect mobility of 6.09 cm(2)/V.s, lower threshold voltage of 3.67 V, larger on/off current ratio above 10(6), and superior current drivability, which can be attributed to the high-quality ZnO thin films with the reduced vertical grain boundaries in the channel region.
CRITICAL CURRENT ANISOTROPY AND FLUX PINNING IN YBCO(001) AND YBCO(110) SUPERCONDUCTING THIN FILMS PREPARED BY KrF PULSED LASER ABLATION
(1993-03-01)
Juang, J. Y.
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Wu, K. H.
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Wang, S. J.
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Lai, T. C.
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Kao, R. T.
Direct transport critical current density (J(C)) measurements were performed on laser ablated high quality Y1Ba2Cu3O7 superconducting thin films with T-CO >= 90 K, J(C) approximate to 5x10(6) A/cm(2) at 77 K, and intentionally controlled film orientations to investigate the J(C) anisotropy and predominant pinning mechanisms in these films. It was found that, for films with (001) oriented normal to the substrate the field dependencies of the critical current densities J(C)(H) showed very different behaviors for different field orientations, indicating that the active pinning mechanisms may be different in two field directions. For the (110) oriented films with field applied normal to film surface, the pinning mechanism, as depicted from the scaling behavior of the global pinning force density, was found to follow the manifestation of surface core pinning. At zero field, however, the temperature dependence of J(C) revealed that, in all cases, the critical current was limited by flux creep with essentially the same creep kinetic factor expected for high-T-C cuprates. Detailed studies of the scaling behaviors of the pinning force density as functions of both field and temperatures for fields up to 7 Tesla will be presented and compared for different films and field orientations.
Flat band voltage control on low V(t) metal-gate/high-kappa CMOSFETs with small EOT
(2009-07-01)
Chin, Albert
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Chang, M. F.
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Lin, S. H.
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Chen, W. B.
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Lee, P. T.
The unwanted high threshold voltage (V(t)) is the major challenge for metal-gate/high-kappa CMOs especially at small equivalent-oxide-thickness (EOT). We have investigated the high V(t) issue that is due to flat-band voltage (V(fb)) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V(fb) roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-kappa CMCSFETs using these methods have achieved low V(t) and good control of V(fb) roll-off at small 0.6-1.2 nm EOT. Crown Copyright (C) 2009 Published by Elsevier B.V. All rights reserved,
Flat band voltage control on low V-t metal-gate/high-kappa CMOSFETs with small EOT
(2009-07-01)
Chin, Albert
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Chang, M. F.
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Lin, S. H.
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Chen, W. B.
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Lee, P. T.
The unwanted high threshold voltage (V-t) is the major challenge for metal-gate/high-kappa CMOs especially at small equivalent-oxide-thickness (EOT). We have investigated the high V-t issue that is due to flat-band voltage (V-fb) roll-off at smaller EOT. A mechanism of charged oxygen vacancies formed by interface reaction was proposed to explain the V-fb roll-off effect. This interface reaction can be decreased by inserting a thin interfacial SiON and using novel low temperature process. The self-aligned and gate-first metal-gate/high-kappa CMCSFETs using these methods have achieved low V-t and good control of V-fb roll-off at small 0.6-1.2 nm EOT. Crown Copyright (C) 2009 Published by Elsevier B.V. All rights reserved,
HfSiON n-MOSFETs using low-work function HfSi chi gate
(2006-09-01)
Wu, C. H.
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Hung, B. F.
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Chin, Albert
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Wang, S. J.
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Yen, F. Y.
The authors have developed a novel high-temperature stable HfSix gate for high-kappa HfSiON gate dielectric. After a 1000 degrees C RTA, the HfSix/HfSiON devices showed an effective work function of 4.27 eV and a peak electron mobility of 216 cm(2)/V (.) s at 1.6-nm equivalent oxide thickness, with additional merit of a process compatible with current very large scale integration fabrication lines.
High temperature stable [Ir3Si-TaN]/HfLaON CMOS with large work-function difference
(2006)
Wu, C. H.
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Hung, B. F.
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Chin, Albert
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Wang, S. J.
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Chen, W. J.
We report novel 1000 degrees C-stable [Ir3Si-TaN]/HfLaON CMOS for the first time, where the self-aligned and gate-first process are full compatible to current VLSI. Good phi(m.eff) of 5.08 and 4.24 eV, low V, of -0.10 and 0.18 V, high mobility of 84 and 217 cm(2)/Vs at 1.6 nm EOT, and small 850 degrees C BTI < 20 mV (10 MV/cm for 1 hr) are measured.
High-Performance InGaZnO Thin-Film Transistors Using HfLaO Gate Dielectric
(2009-12-01)
Su, N. C.
;
Wang, S. J.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, we report a low-voltage-driven amorphous indium-gallium-zinc oxide thin-film transistor with a high-k-value HfLaO gate dielectric. Good characteristics were achieved including a low V(T) of 0.22 V, small subthreshold swing of 76 mV/dec, high mobility of 25 cm(2)/V . s, and large I(on)/I(off) ratio of 5 x 10(7). These good performances are obtained at an operation voltage as low as 2 V. These characteristics are attractive for high-switching-speed and low-power applications.
High-temperature stable HfLaON p-MOSFETs with high-work-function Ir3Si gate
(2007-04-01)
Wu, C. H.
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Hung, B. F.
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Chin, Albert
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Wang, S. J.
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Wang, X. P.
We report a novel 1000 degrees C stable HfLaON p-MOSFET with Ir3Si gate. Low leakage current of 1.8 x 10(-5) A/cm(2) at 1 V above flat-band voltage, good effective work function of 5.08 eV, and high mobility of 84 cm(2)/V center dot s are simultaneously obtained at 1.6 nm equivalent oxide thickness. This gate-first p-MOSFET process with self-aligned ion implant and 1000 degrees C rapid thermal annealing is fully compatible to current very large scale integration fabrication lines.
High-temperature stable IrxSi gates with high work function on HfSiON p-MOSFETs
(2007-02-01)
Hung, B. F.
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Wu, C. H.
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Chin, Albert
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Wang, S. J.
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Yen, F. Y.
A novel 1000 degrees C-stable IrxSi gate on HfSiON is shown for the first time with full process compatibility to current very-large-scale-integration fabrication lines and proper effective work function of 4.95 eV at 1.6-nm equivalent-oxide thickness. In addition, small threshold voltages and good hole mobilities are measured in IrxSi/HfSiON transistors. The 1000 degrees C thermal stability above pure metal (900 degrees C only) is due to the inserted 5-nm amorphous Si, which also gives less Fermi-level pinning by the accumulated metallic full silicidation at the interface.
HtLaON n-MOSFETs using a low work function HfSix gate
(2007-12-01)
Cheng, C. F.
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Wu, C. H.
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Su, N. C.
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Wang, S. J.
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McAlister, S. P.
At a 1.2-nm equivalent oxide thickness, HfSix/Hf0.7La0.3ON n-MOSFETs showed an effective work function of 4.33 eV, a low threshold voltage of 0.18 V, and a peak electron mobility of 215 cm(2)/(V center dot s). These self-aligned and gate-first HfSix/Hf0.7La0.3ON n-MOSFETs were processed using standard ion implantation and 1000-degrees C rapid thermal annealing, making them fully compatible with current very large scale integration fabrication lines.
Low threshold voltage and high drive current poly-silicon thin film transistors using Ytterbium metal gate and LaAlO3 dielectric
(2007)
Hung, B. F.
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Wu, C. H.
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Chin, Albert
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Wang, S. J.
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Lin, J. W.
We have demonstrated high-performance metal-gate/high-k Ytterbiuni/LaAlO3 low-temperature poly-Si (LTPS) thin film transistors (TFTs) that have both high drive current capability and high voltage operation. The high drive current is due to the combined effect of low work-function Ytterbium metal gate and high gate capacitance by high-k LaAlO3 dielectric. The high breakdown voltage is also due to the high-k LaAlO3 dielectric to give larger physical thickness at the same equivalent oxide thickness (EOT). The good reliability and full process compatibility are the other important merits for Ytterbium/LaAlO3 device.
Low V-t gate-first Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection
(2008)
Liao, C. C.
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Chin, Albert
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Su, N. C.
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Li, M. -F.
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Wang, S. J.
We report low V-t Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection with self-aligned and gate-first process compatible with current VLSI. At 1.05 nm EOT, good phi(ro-eff) of 5.04 and 4.24 eV, low V-t of -0.16 and 0.13 V, high mobility of 85 and 209 cm(2)/Vs, and small 85 degrees C BTI <= 40 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
Low V-t gate-first Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection
(2008-01-01)
Liao, C. C.
;
Chin, Albert
;
Su, N. C.
;
Li, M. -F.
;
Wang, S. J.
We report low V-t Al/TaN/[Ir3Si-HfSi2-x]/HfLaON CMOS using simple laser annealing/reflection with self-aligned and gate-first process compatible with current VLSI. At 1.05 nm EOT, good phi(m-eff) of 5.04 and 4.24 eV, low V-t of -0.16 and 0.13 V, high mobility of 85 and 209 cm(2)/Vs, and small 85 degrees C BTI <= 40 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.
Very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low temperature shallow junctions
(2007)
Cheng, C. F.
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Wu, C. H.
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Su, N. C.
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Wang, S. J.
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McAlister, S. P.
We report very low V(t) [Ir-Hf]/HfLaO CMOS using novel self-aligned low-temperature ultra shallow junctions with gate-first process compatible with current VLSI. At 1.2 nm EOT, good phi(m-eff) of 5.3 and 4.1 eV, low V(t) of +0. 05 and 0.03 V, high mobility of 90 and 243 cm(2)/Vs, and small 85 degrees C BTI <32 mV (10 MV/cm, 1 hr) are measured for p- and n-MOS.