Browsing by Author "Wang, Shih-Hsing"

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A 0.35-V 240-W Fast-Lock and Low-Phase-Noise Frequency Synthesizer for Implantable Biomedical Applications
(2019-12-01)
Wang, Shih-Hsing
;
Hung, Chung-Chih
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
For implantable frequency synthesizers, realizing ultra-low voltage (ULV) and low power in addition to meeting PLL targets, fast lock and low phase noise, poses a difficult challenge. This paper presents techniques to achieve PLL targets as well as ULV and low power in the same chip through the use of a regular CMOS technology node. A curvature-PFD technique achieves both faster locking and lower jitter compared with conventional techniques. A two-step switching technique substantially reduces the power consumption in current mirrors and reduce noise when switching from a charge pump. Leakage analysis and subthreshold-leakage-reduction technique reduce reference spur and jitter to the voltage-controlled oscillator (VCO). A dither technique randomizes and averages reference spurs. The proposed chip was implemented in 90-nm CMOS technology; the 0.35-V medical-band frequency synthesizer consumes 238-W power while generating output clock of 401.8 to 431.31-MHz and exhibiting a phase noise of -105.7 dBc/Hz at 1-MHz frequency offset with 20 s locking time.
A 0.3V 10b 3MS/s SAR ADC With Comparator Calibration and Kickback Noise Reduction for Biomedical Applications
(2020-06-01)
Wang, Shih-Hsing
;
Hung, Chung-Chih
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper presents a 10-bit successive approximation analog-to-digital converter (ADC) that operates at an ultralow voltage of 0.3 V and can be applied to biomedical implants. The study proposes several techniques to improve the ADC performance. A pipeline comparator was utilized to maintain the advantages of dynamic comparators and reduce the kickback noise. Weight biasing calibration was used to correct the offset voltage without degrading the operating speed of the comparator. The incorporation of a unity-gain buffer improved the bootstrap switch leakage problem during the hold period and reduced the effect of parasitic capacitances on the digital-to-analog converter. The chip was fabricated using 90-nm CMOS technology. The data measured at a supply voltage of 0.3 V and sampling rate of 3 MSps for differential nonlinearity and integral nonlinearity were +0.83/-0.54 and +0.84/-0.89, respectively, and the signal-to-noise plus distortion ratio and effective number of bits were 56.42 dB and 9.08 b, respectively. The measured total power consumption was 6.6 mu W at a figure of merit of 4.065 fJ/conv.-step.