Browsing by Author "Wang, Shih-Jung"

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A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
(2009)
Lee, Yu-Huei
;
Wang, Shih-Jung
;
Yang, Yao-Yi
;
Zheng, Kuo-Lin
;
Chen, Po-Fung
The proposed power management module with 1 V low-voltage PWM controller and dynamic self-biasing mechanism is designed to integrate with ultra-wide band (UWB) system. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Instead of using large external compensation circuit, the compensation enhancement multistage amplifier increases system loop gain and stabilizes the system. Moreover, the proposed self-biasing mechanism enhances the power conversion efficiency by 4 % through the handover technique. The fabricated power management module occupies 0.356 mm(2) silicon in 65nm CMOS. With the excellent line/load transient response and the highest efficiency about 93.5%, the proposed power management has the qualification to be integrated in today's system-on-chip (SoC) applications.
A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System
(2010-11-01)
Lee, Yu-Huei
;
Yang, Yao-Yi
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
;
Wang, Shih-Jung
The proposed power management module with a typical 1.2 V low-voltage PWM (LV-PWM) controller and dynamic voltage scaling (DVS) function is designed using 65 nm technology for integration with the ultra-wide band (UWB) system. The on-chip pre-regulator with a power conditioning circuit can provide a regulated supply voltage to the LV-controller. Moreover, the proposed handover technique can achieve the self-biasing mechanism to further reduce power dissipation. To operate in low voltage, the proposed compensation enhancement multistage amplifier (CEMA) can achieve high loop gain and ensure system stability without using any external compensation component. The fabricated power management module occupies 0.356 mm(2) silicon area with an excellent line/load transient response. Owing to the DVS function, the proposed power management can meet the power requirement in the UWB system and other RF transceiver systems.
A High Efficiency and Compact Size 65nm Power Management Module with 1.2V Low-Voltage PWM Controller for UWB System Application
(2009)
Lee, Yu-Huei
;
Wang, Shih-Jung
;
Yang, Yao-Yi
;
Zheng, Kuo-Lin
;
Chen, Po-Fung
This 65 nm power management module with 1.2 V low-voltage PWM controller aims to integrate with ultra-wideband (UWB) system to get high efficiency and compact size. The on-chip pre-regulator with power conditioning circuit provides a constant and noiseless supply voltage. Thus, the voltage variation of battery has less effect on the low-voltage PWM controller. The proposed compensation enhancement multistage amplifier (CEMA) increases system loop gain and stabilizes the system without off-chip compensation circuit. With excellent line/load transient response, the proposed power management has the highest efficiency about 92% and 0.995 mm(2) silicon die area.
An Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters with 91% Peak Efficiency
(2010)
Lee, Yu-Huei
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
;
Yang, Yao-Yi
;
Wang, Shih-Jung
This interleaving energy-conservation mode control for single-inductor dual-output converter uses the superposition technique to yield the optimal average inductor current and 91% peak efficiency. Neither a freewheel stage nor a post-regulator is needed at nominal conditions. The output voltage ripple appears notably minimized over 50% by means of current interleaving at full load. The chip occupies 1.44 mm(2) in 65 nm CMOS and integrates with a 3D architecture for ultra-wide band system.
Current mode DC-DC buck converters with optimal fast-transient control
(2008)
Lee, Yu-Huei
;
Wang, Shih-Jung
;
Hsieh, Chun-Yu
;
Chen, Ke-Horng
;
電控工程研究所
A load dependent proportional-integration (PI) compensation is proposed in this paper for minimizing transient dropout voltage and accelerating the transient response of current mode DC-DC converters. The adaptive compensation resistance and capacitance are used to react to the sudden load variations: At the beginning of load transient response, the adaptive compensation capacitance is decreased to move the compensation pole-zero pair to a higher frequency for achieving fast transient response. At the end of load transient response, the pole-zero pair is moved back to an optimal position for extending the system bandwidth and phase margin based on the instant load condition. Simulation results demonstrate the excellent performance at transient period and steady-state with this proposed fast transient control and adaptive pole-zero compensation. The overshoot/undershoot voltage is smaller than 45mV and transient period is shorter than 15us as load current suddenly changes between 100mA and 500mA.
High efficiency and/or low cost LED backlight system for color sequential technique in color filter-less LCD system
(2008)
Hsieh, Chun-Yu
;
Wang, Shih-Jung
;
Lee, Yu-Huei
;
Chen, Ke-Horng
;
Ho, Ming-Tsung
This paper proposes a design methodology for implementing a high efficiency and/or a low cost RGB backlight module in color sequential notebook computers' display. A RGB LED driver composed of an asynchronous 1.5MHz DC/DC boost converter with dual loop control is fabricated by TSMC 0.25 mu m BCD 40V to generate 17V or 21V output voltage to turn on more than 6 series-red, 6 series-green, or series-blue LEDs at the same time for the notebooks' backlight. Besides, charge-recycling technique is used to restore extra energy at the output node when switching to different forwarding light emitting diodes (LEDS) and release the energy new time. The total power consumption of a 15.4' LCD panel of a notebook computer can be reduced from 5W to about 2-3 W.
Interleaving Energy-Conservation Mode (IECM) Control in Single-Inductor Dual-Output (SIDO) Step-Down Converters With 91% Peak Efficiency
(2011-04-01)
Lee, Yu-Huei
;
Yang, Yao-Yi
;
Wang, Shih-Jung
;
Chen, Ke-Horng
;
Lin, Ying-Hsi
The proposed single-inductor dual-output (SIDO) converter with interleaving energy-conservation mode (IECM) control is designed using 65 nm technology to power the ultra-wide band (UWB) system. The energy-conservation mode (ECM) control generates four different energy delivery paths for dual buck outputs with only one inductor. In addition, the superposition technique is used to achieve a minimized inductor current level. The average inductor current is equal to the summation of two output loads. Moreover, the IECM control activates the interleaving operation through the current interleaving mechanism to provide large driving capability as well as to reduce the output voltage ripple. As a result, 91% peak efficiency is derived and the output voltage ripple appears notably minimized by 50% using current interleaving at heavy load. The test chip occupies 1.44 mm(2) in 65 nm CMOS and integrates with a three-dimensional (3-D) architecture for inductor integration.
LED drivers with PPD compensation for achieving fast transient response
(2008)
Hsieh, Chun-Yu
;
Wang, Shih-Jung
;
Lee, Yu-Huei
;
Chen, Ke-Horng
;
電控工程研究所
A trade-off performance between static error and dynamic response is made by the combination of proportional (P) and proportional derivative (PD) compensations. Owing to the fast transient response provided by the P compensator, the static error is also reduced by the PD compensator within a reasonable response time. The proposed control circuit is entirely implemented by voltage mode and has better line and load regulations. An asynchronous 1.8MHz DC/DC boost converter was fabricated by UMC 0-35 mu m to generate 35V output voltage to turn on more than 10 LED at the same time for the notebook's backlight.
Quadratic Differential and Integration Technique in V(2) Control Buck Converter with Small ESR Capacitor
(2009)
Wang, Shih-Jung
;
Lee, Yu-Huei
;
Lai, Yung-Chih
;
Chen, Ke-Horng
;
電控工程研究所
This paper proposes a quadratic differential and integration (QDI) technique for the design of buck converters with small equivalent series resistance (ESR) of the output capacitor. The QDI circuit not only further removes the dependence of ESR in the V(2) control but also achieves a fast transient response with small load transient voltage variation. The experimental results show the output voltage can have voltage ripple about 30 mV and recovery time of 20 Its in case of 300 mA load current variation.
Quadratic Differential and Integration Technique in V(2) Control Buck Converter With Small ESR Capacitor
(2010)
Lee, Yu-Huei
;
Wang, Shih-Jung
;
Chen, Ke-Horng
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper proposes a quadratic differential and integration (QDI) technique for the design of V(2) control buck converters with small equivalent series resistance (ESR) of the output capacitor. The QDI technique, which eliminates the use of large ESR in the V(2) control structure, achieves the fast transient response with the small output voltage variation in transient period. Besides, the precise sensing signal is derived from the QDI circuit without the unwilling ESR-related distortion. Moreover, the loop analysis demonstrates that the proposed QDI circuit and the proportional and integral compensator can generate the compensation zero pair to stabilize the system. Experimental results show that the output voltage has small voltage ripple opposite to the conventional V(2) control. In load transient period, the overshoot/undershoot voltage is smaller than 40 mV when output voltage is 2 V, and the transient recovery time inheriting the advantage of V(2) control is shorter than 9 mu s with the load step from 100 to 400 mA and vice versa. The highest full chip power conversion efficiency is about 93%.
Quadratic Differential and Integration Technique in V-2 Control Buck Converter With Small ESR Capacitor
(2010-04-01)
Lee, Yu-Huei
;
Wang, Shih-Jung
;
Chen, Ke-Horng
;
電控工程研究所
;
Institute of Electrical and Control Engineering
This paper proposes a quadratic differential and integration (QDI) technique for the design of V-2 control buck converters with small equivalent series resistance (ESR) of the output capacitor. The QDI technique, which eliminates the use of large ESR in the V-2 control structure, achieves the fast transient response with the small output voltage variation in transient period. Besides, the precise sensing signal is derived from the QDI circuit without the unwilling ESR-related distortion. Moreover, the loop analysis demonstrates that the proposed QDI circuit and the proportional and integral compensator can generate the compensation zero pair to stabilize the system. Experimental results show that the output voltage has small voltage ripple opposite to the conventional V-2 control. In load transient period, the overshoot/undershoot voltage is smaller than 40 mV when output voltage is 2 V, and the transient recovery time inheriting the advantage of V-2 control is shorter than 9 mu s with the load step from 100 to 400 mA and vice versa. The highest full chip power conversion efficiency is about 93%.
Sub-1V Input Single-Inductor Dual-Output (SIDO) DC-DC Converter with Adaptive Load-Tracking Control (ALTC) for Single-Cell-Powered System
(2009)
Huang, Ming-Hsin
;
Tsai, Yu-Nong
;
Lee, Yu-Huei
;
Wang, Shih-Jung
;
Chen, Ke-Horng
In this paper, a sub-1V input single-inductor dual-output (SIDO) DC-DC converter with an adaptive load-tracking control (ALTC) technique is proposed for single-cell-powered portable devices. The ALTC technique adaptively and accurately adjusts storage charge in form of the inductor current according to actual load condition without wasting surplus charge and increasing cross-regulation through the use of minimized the number of switch and optimum current sequence. A current-mode ring oscillator with a self-bias current source (SBCS) circuit is proposed to replace conventional startup oscillator to produce a nearly constant system clock. The test chip was fabricated by TSMC 0.25 mu m 2.5 V/5 V BCD process and experimental results show a high efficiency of 92 % and a cross- regulation smaller than 10 mV.