Browsing by Author "Wang, Tahui"

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A Comparative Study of NBTI and RTN Amplitude Distributions in High-kappa Gate Dielectric pMOSFETs
(2012-02-01)
Chiu, J. P.
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Chung, Y. T.
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Wang, Tahui
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Chen, Min-Cheng
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Lu, C. Y.
Random telegraph noise (RTN) and negative bias temperature (NBT) stress-induced threshold voltage (V-t) fluctuations in high-kappa gate dielectric and metal-gate pMOSFETs are investigated. We measured RTN amplitude distributions before and after NBT stress. RTN in poststressed devices exhibits a broader amplitude distribution than the prestress one. In addition, we trace a single trapped charge-induced Delta V-t in NBT stress and find that the average Delta V-t is significantly larger than a Delta V(t)caused by RTN. A 3-D atomistic simulation is performed to compare a single-charge-induced Delta V-t by RTN and NBTI. In our simulation, the probability distribution of a NBT trapped charge in the channel is calculated from the reaction-diffusion model. Our simulation confirms that the NBT-induced Delta V-t indeed has a larger distribution tail than RTN due to a current-path percolation effect.
A Novel Hot-Electron Programming Method in a Buried Diffusion Bit-Line SONOS Memory by Utilizing Nonequilibrium Charge Transport
(2009-02-01)
Wang, Tahui
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Tang, Chun-Jung
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Li, C. -W.
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Lee, Chih Hsiung
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Ou, T. -F
We propose a new hot-electron programming method with a low drain-to-source voltage in a buried-diffusion (BD) bit-line SONOS memory array. In this method, channel electrons are preaccelerated in a cell preceding a program cell. For a small bit-line width, some energetic electrons will traverse an n(+) BD region and enter a program cell with residual energy due to nonequilibrium transport. Our measurement result shows that this residual energy can significantly enhance hot-electron programming efficiency even at a V(ds) of 2.5 V. The concept of this method is verified by means of a Monte Carlo analysis. Our study shows that this method is more effective as a bit-line width reduces.
A Novel Random Telegraph Signal Method to Study Program/Erase Charge Lateral Spread and Retention Loss in a SONOS Flash Memory
(2011-03-01)
Ma, Huan-Chi
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Chou, You-Liang
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Chiu, Jung-Piao
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Chung, Yueh-Ting
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Lin, Tung-Yang
A novel random telegraph signal (RTS) method is proposed to characterize the lateral distribution of injected charge in program and erase states in a NOR-type silicon-oxide-nitride-oxide-silicon Flash memory. The concept of this method is to use RTS to extract an oxide trap position in the channel and then to use the trap and RTS as internal probe to detect a local channel potential change resulting from injected charge during program/erase. By using this method, the lateral width of the injected charge-induced channel potential barrier is shown to be around 20 nm in channel hot electron (CHE) program. Our method also confirms that Channel Initiated Secondary ELectron (CHISEL) program has a broader injected charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band tunneling erase holes is observed. Program-state V(t) retention loss models, charge vertical loss versus lateral migration, are reexamined by using this method. The polarity of a program-state charge distribution along the channel is explored within 10-20 program/erase cycles. Nitride charge vertical loss is verified by this method.
A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
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Li, Kai-Shin
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Li, Lain-Jong
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Li, Ming-Yang
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Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory
(2018-01-01)
Lu, C. C.
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Cheng, C. C.
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Chiu, H. P.
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Lin, W. L.
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Chen, T. W.
Feasibility of multi-times verify (MTV) scheme on triple-level cell (TLC) and quad-level cell (QLC) operations of charge-trap storage 3D NAND memories is investigated comprehensively. Results reveal that random telegraph noise (RTN) and program noise are the major factors affecting lower (LB) and upper boundaries (HB) of Vt distribution, respectively. Enlargement of operation window and reduction of ECC usage with MTV scheme to mitigate RTN-induced LB tail are demonstrated on TLC and QLC operations. In addition, the impact of program noise on HB Vt under various process conditions and ISPP steps is studied experimentally and also explained by our Monte Carlo simulator. Finally, program performance and reserved margin with and without MTV scheme applied on TLC and QLC operation are demonstrated.
Analytical Modeling of Read-Induced SET-State Conductance Change in a Hafnium-Oxide Resistive Switching Device
(2020-01-01)
Su, Po-Cheng
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Jiang, Cheng-Min
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Chen, Yu-Jia
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Wang, Chih-Chieh
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Li, Kai-Shin
A SET-state conductance change in a hafnium-oxide resistive switching memory cell due to repeated read events is investigated. We characterize a read-induced conductance change at different read voltages and SET-state conductance levels. Our result shows that the read-induced conductance degradation exhibits a two-stage evolution with the read pulse number. A SET-state conductance decreases slightly in the first stage and then follows inverse power-law dependence on the read number in the second stage. The power factor is an exponential function of a read voltage without regard to the SET-state conductance level, and the read pulse number at the transition of the two stages is related to a read voltage and conductance level. An analytical model to describe the two-stage conductance evolution is proposed. The parameters in the model are extracted from measurement data. Our model is verified by good agreement between the modeled and measured results in a wide range of read pulse number, read voltage, and SET-state conductance level.
<bold>Read Current Instability Arising from Random Telegraph Noise in Localized Storage, Multi-Level SONOS Flash Memory</bold>
(2006)
Gu, S. H.
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Li, C. W.
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Wang, Tahui
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Lu, W. P.
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Chen, K. C.
Program/erase cycling stress induced read current fluctuations arising from random telegraph noise (RTN) in a localized storage, multi-level nitride flash memory (SONOS) is explored. Our study shows that localized charge storage significantly enhances RTN. The amplitude of RTN varies in different program levels of a multi-level cell. The broadening of read current distribution due to RTN is characterized and modeled. Improvement of bottom oxide robustness can reduce the read current fluctuations.
Cell Endurance Prediction from a Large-area SONOS Capacitor
(2009)
Lee, C. H.
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Tu, W. H.
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Gu, S. H.
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Wu, C. W.
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Lin, S. W.
Endurance considerations induced by the degadation of top and bottom oxides are proposed for a SONOS memory. First, a correlation is found between the widespread C-V curves induced by interface generation and cycling numbers (cyc. #). Unlike V-FB (accumulation region), V-T (inversion region) shows a much severe shift. Inter-face state (N-it) is identified as a key factor even when a 2nm bottom oxide is used. Moreover, charge to breakdown (Q(BD)) for an ONO capacitor under positive and negative constant current stress (CCS) is investigated. Our study reveals that QBD of such stacks strongly depends on the top oxide thickness. A field enhancement induced by charges in a trapping nitride layer is the root cause. Based on Weibull statistics, the risk of dielectric breakdown for both blocking layers is then evaluated.
Characteristics and physical mechanisms of positive bias and temperature stress-induced drain current degradation in HfSiON nMOSFETs
(2006-06-01)
Chan, Chien-Tai
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Tang, Chun-Jung
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Wang, Tahui
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Wang, Howard C. -H.
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Tang, Denny D.
Drain current degradation in HfSiON gate, dielectric nMOSFETs by positive gate bias and temperature stress is investigated by using a fast transient measurement technique. The degradation exhibits two stages, featuring a different degradation rate and stress temperature dependence. The first-stage degradation is attributed to the charging of preexisting high-k dielectric traps and has a log(t) dependence on stress time, whereas the second-stage degradation is mainly caused by new high-k trap creation. The high-k trap growth rate is characterized by two techniques, namely 1) a recovery transient technique and 2) a charge-pumping technique. Finally, the effect of processing on high-k trap growth is evaluated.
Characterization and modeling of SET/RESET cycling induced read-disturb failure time degradation in a resistive switching memory
(2017-12-07)
Su, Po-Cheng
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Hsu, Chun-Chi
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Du, Sin-I
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Wang, Tahui
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電機學院
Read operation induced disturbance in SET-state in a tungsten oxide resistive switching memory is investigated. We observe that the reduction of oxygen vacancy density during read-disturb follows power-law dependence on cumulative read-disturb time. Our study shows that the SET-state read-disturb immunity progressively degrades by orders of magnitude as SET/RESET cycle number increases. To explore the cause of the read-disturb degradation, we perform a constant voltage stress to emulate high-field stress effects in SET/RESET cycling. We find that the read-disturb failure time degradation is attributed to high-field stress-generated oxide traps. Since the stress-generated traps may substitute for some of oxygen vacancies in forming conductive percolation paths in a switching dielectric, a stressed cell has a reduced oxygen vacancy density in SET-state, which in turn results in a shorter read-disturb failure time. We develop an analytical read-disturb degradation model including both cycling induced oxide trap creation and read-disturb induced oxygen vacancy reduction. Our model can well reproduce the measured read-disturb failure time degradation in a cycled cell without using fitting parameters. Published by AIP Publishing.
Characterization and modeling of trap number and creation time distributions under negative-bias-temperature stress
(2012-08-20)
Chiu, Jung-Piao
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Li, Chi-Wei
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Wang, Tahui
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Individual trapped charge creations and a trap number in p-type metal-oxide-semiconductor field effect transistors (pMOSFETs) under negative bias temperature instability (NBTI) stress are investigated. We find that the characteristic times of a trapped charge creation scatter over several decades of time in small area pMOSFETs, which is attributed to an activation energy distribution in the reaction-diffusion (RD) model of NBTI. We develop a statistical model by combining the RD model with an extracted activation energy distribution to calculate a threshold voltage shift distribution at different NBTI stress times. Our model agrees with measured results very well. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4748108]
Characterization and Monte Carlo analysis of secondary electrons induced program disturb in a buried diffusion bit-line SONOS flash memory
(2007)
Tang, Chun-Jung
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Li, C. W.
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Wang, Tahui
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Gu, S. H.
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Chen, P. C.
A new program disturb in a buried diffusion bit-line SONOS array is observed as a bit-line width is reduced. A multi-step Monte Carlo simulation is performed to explore the disturb mechanism. We find that the V, shift of a disturbed cell is attributed to impact ionization-generated secondary electrons in a neighboring cell when it is in programming. The effects of substrate bias, bit-line dimension and pocket implant on the program disturb are characterized and evaluated by a Monte Carlo simulation.
Characterization of nitride hole lateral transport in a charge trap flash memory by using a random telegraph signal method
(2017-07-17)
Liu, Yu-Heng
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Jiang, Cheng-Min
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Lin, Hsiao-Yi
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Wang, Tahui
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Tsai, Wen-Jer
We use a random telegraph signal method to investigate nitride trapped hole lateral transport in a charge trap flash memory. The concept of this method is to utilize an interface oxide trap and its associated random telegraph signal as an internal probe to detect a local channel potential change resulting from nitride charge lateral movement. We apply different voltages to the drain of a memory cell and vary a bake temperature in retention to study the electric field and temperature dependence of hole lateral movement in a nitride. Thermal energy absorption by trapped holes in lateral transport is characterized. Mechanisms of hole lateral transport in retention are investigated. From the measured and modeled results, we find that thermally assisted trap-to-band tunneling is a major trapped hole emission mechanism in nitride hole lateral transport. Published by AIP Publishing.
Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
(2018-01-01)
Lin, T. W.
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Ku, S. H.
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Cheng, C. H.
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Lee, C. W.
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Ijen-Huang
Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a "Gaussian-like" shape rapidly and was measured by the self established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.
Correlation between SET-State Current Level and Read Disturb Failure Time in a Resistive Switching Memory
(2018-01-01)
Su, P. C.
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Jiang, C. M.
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Wang, C. W.
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Wang, Tahui
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電子工程學系及電子研究所
The relationship between SET-state current level and read-disturb failure time in a tungsten oxide RRAM is characterized and modeled. Our result shows that read voltage induced reduction of oxygen vacancy density in tungsten oxide follows a power law dependence on cumulative read-disturb time. The power factor is independent of SET-state current level. Read disturb failure time is considerably improved by several orders of magnitude as SET-state current level increases a few times. An analytical model to correlate SET-state current level and read disturb failure time is proposed. Since SET-state current level is related to a cross-section of a conductive filament in an oxide, our model is developed based on a relationship between oxide area and critical oxide trap (oxygen vacancy) density from an oxide breakdown model. The validity of the proposed model is supported by experiment results.
Cycling-Induced SET-Disturb Failure Time Degradation in a Resistive Switching Memory
(2015-02-01)
Chung, Yueh-Ting
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Su, Po-Cheng
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Cheng, Yu-Hsuan
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Wang, Tahui
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Chen, Min-Cheng
A new degradation mode with respect to write-disturb failure time due to SET/RESET cycling in a tungsten oxide resistive random access memory is reported. In a crossbar array memory, we find that a write-disturb failure time in high resistance state reduces suddenly by several orders of magnitude after certain SET/RESET cycles. This abrupt degradation is believed due to the creation of a new soft breakdown path in a switching dielectric by cycling stress. Although a memory window still remains after the degradation, the occurrence probability of over-SET state increases significantly. This cycling-induced degradation mode imposes a serious constraint on the number of SET-disturb pulses and thus an endurance cycle number in a resistive switching memory.
Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector-MTJ Cooptimization
(2020-08-01)
Chiang, Hung-Li
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Chen, Tzu-Chiang
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Song, Ming-Yuan
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Chen, Yu-Sheng
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Chiu, Jung-Piao
To increase the density of magnetoresistive random accessmemory (MRAM) beyond the 1T1MTJMRAM cell in use today, the design space for 1S1MTJ MRAM array is analyzed by cooptimizing both selectors and MTJs. Current low-resistance MTJs for 1T1MTJ MRAM are not suitable for 1S1MTJ MRAM. Threshold-type selectors would induce a strong read disturb on the MTJ due to the snapback voltage (V-TH-V-HOLD) when the selector is turned on. Also, exponential-type selectorswould degrade the read margin (RM) due to its large ON-state resistance. When using existing selectors to achieve a 1-M-bit 1S1MTJ array, it is necessary to adjust the product of resistance and area (RA) and the diameter of the MTJ. An MTJ with the RA = 15 Omega . mu m(2) and the diameter = 50 nm can meet the criterion of RM > 10% for both exponential-type selectors (exponential slope = 300-500 mV/decade with the current density similar to 1 MA/cm(2)) and threshold-type selectors (V-TH-V-HOLD similar to 250 mV). A design space accommodating a selector variation of around 1% can be found for MTJs with tunnel magnetoresistance ratio (TMR) < 250%. With an increased TMR of 250%-350% of the MTJ, the tolerance of variations for exponential-type selectors and threshold-type selectors can be improved to 2% and 4%, respectively. This provides a chance for the 1S1MTJ MRAM with existing selectors.
Effects of length scaling on electromigration in dual-damascene copper interconnects
(2008-04-01)
Lin, M. H.
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Lin, M. T.
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Wang, Tahui
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
The electromigration short-length effect in dual-damascene Cu interconnects has been investigated through experiments on lines of various lengths (L), being stressed at a variety of current densities (j), and using a technologically realistic three-level structure. This investigation represents a complete study of the short-length effect after a well-developed dual-damascene Cu process. Lifetime measurement and resistance degradation as a function of time were used to describe this phenomenon. It has been found that the sigma of log-normal distribution increased as the current density-length product decreased. The statistical distribution of the critical volume fits the sigma curve well. Lower jL(2) values show large sigma values because of back-stress-induced TTF (time-to-fail) dispersion. A simplified equation is proposed to analyze the experimental data from various combinations of current density and line length at a certain temperature. The resulting threshold-length product (jL)(C) value appears to be temperature dependent, decreasing with an increase in temperature in a range of 250-300 degrees C. (c) 2007 Elsevier Ltd. All rights reserved.
Effects of width scaling and layout variation on dual damascene copper interconnect electromigration
(2007-12-01)
Lin, M. H.
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Chang, K. P.
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Su, K. C.
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Wang, Tahui
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電子工程學系及電子研究所
Electromigration versus line width in the 0.12-10 mu m range and the configuration of the via/line contact in dual damascene Cu has been investigated. There are two scenarios for width scaling impact on electromigration. One is the width < 1 mu m region, in which the MTF shows a weak width dependence, except for the via-limited condition. The other is the width > 1 mu m region, in which the MTF shows a strong width dependence. A theory was proposed to explain the observed behavior. For polycrystalline lines (width > 1 mu m), the dominant diffusion paths are a mixture of grain boundary and surface diffusion. The activation energy for the dominant grain boundary transport (width > 1 mu m) is approximately 0.2 eV higher than that of the dominant surface transport (width similar to 1 mu m). The derived activation energies for grain-boundary and surface diffusion are obtained from Cu drift velocity under electromigration stressing. The mechanisms governing the electromigration lifetime of interconnects leads to via interconnect design rules for maximizing lifetime being identified. (C) 2006 Elsevier Ltd. All rights reserved.
Effects of width scaling, length scaling, and layout variation on electromigrationin in dual damascene copper interconnects
(2006)
Lin, M. H.
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Chang, K. P.
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Su, K. C.
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Wang, Tahui
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電子工程學系及電子研究所