Browsing by Author "Wang, Wen-Chieh"

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45-nm Planar Bulk-CMOS 23-GHz LNAs With High-Q Above-IC Inductors
(2010)
Wang, Wen-Chieh
;
Huang, Zue-Der
;
Carchon, Geert
;
Mercha, Abdelkarim
;
Decoutere, Stefaan
Two 23 GHz low-noise amplifier (LNA) have been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNAs, the structure of cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging (WLP) technology. The fabricated one-stage LNA has a good linearity where the input 1 dB compression point (IP(-1dB)) is -9.5 dBm and the input referred third-order intercept point (P(IIP3)) is +2.25 dBm. It is operated with a 1 V power supply drawing a current of only 3.6 mA. The fabricated one-stage LNA has demonstrated a 4 dB noise figure (NF) and a 7.1 dB gain at the peak gain frequency of 23 GHz. Moreover, the fabricated two-stage LNA has the IP(-1dB) of -16 dBm and the P(IIP3) of -4.2 dBm. It drains 9.3 mA from 1-V power supply. This two-stage LNA has demonstrated a 4.4 dB NF and a 11.6 dB gain at the peak gain frequency of 23.4 GHz. The fabricated one-stage LNA has the highest figure-of-merit (FOM). The experimental results have proved the suitability of 45 nm gate length planar bulk-CMOS devices for RF ICs above 20 GHz.
A 1 V 23 GHz Low-Noise Amplifier in 45 nm Planar Bulk-CMOS Technology With High-Q Above-IC Inductors
(2009-05-01)
Wang, Wen-Chieh
;
Huang, Zue-Der
;
Carchon, Geert
;
Mercha, Abdelkarim
;
Decoutere, Stefaan
A 23 GHz electrostatic discharge-protected low-noise amplifier (LNA) has been designed and implemented by 45 nm planar bulk-CMOS technology with high-Q above-IC inductors. In the designed LNA, the structure of a one-stage cascode amplifier with source inductive degeneration is used. All high-Q above-IC inductors have been implemented by thin-film wafer-level packaging technology. The fabricated LNA has a good linearity where the input I dB compression point (IP(-1) (dB))is - 9.5 dBm and the input referred third-order intercept point (P(IIP3)) is +2.25 dBm. It is-operated with a I V power supply drawing a current of only 3.6 mA. The fabricated LNA has demonstrated a 4 dB noise figure and a 7.1 dB gain at the peak gain frequency of 23 GHz, and it has the highest figure-of-merit. The experimental results have proved the suitability of 45 nm gate length bulk-CMOS devices for PF ICs above 20 GHz.
A 1.5-V 3 similar to 10-GHz 0.18-mu m CMOS Frequency Synthesizer for MB-OFDM UWB Applications
(2008)
Huang, Zue-Der
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Kuo, Fong-Wei
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Wang, Wen-Chieh
;
Wu, Chung-Yu
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電子工程學系及電子研究所
An Ultra wide band (UWB) frequency synthesizer is designed and fabricated in 0.18-mu m CMOS technology to generate all the carrier frequencies for 13 bands distributed from 3 to 10 GHz. It is composed of one phase-locked loop (PLL) and three single-side band (SSB) mixers. The polyphase filter is used to generate all needed quadrature signals in the circuit and band selectors are to select the frequency band. The sideband rejection can be over 30dB. The switching time between bands is around 3.75ns. The current consumption is 72mA under 1.5-V power supply.
A 24-GHz CMOS current-mode power amplifier with high PAE and output power
(2007)
Wu, Chung-Yu
;
Hsu, Shun-Wei
;
Wang, Wen-Chieh
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new 24-GHz CMOS current-mode power amplifier in 0.13-mu m CMOS technology is proposed. By using the two-stage cascade current-mirror structure, the power amplifier has a maximum output power of 17.8 dBm, the 0P(1dB) of 13.8 dBm and the power gain of 23 dB under the supply voltage of 1.2V and the total power dissipation of 239 mW. As compared to other PAs at 17 similar to 24 GHz the proposed current-mode PA has the highest power added efficiency (PAE) of 34.6% and the largest output power.
A Low-Power K-Band CMOS Current-Mode Up-Conversion Mixer Integrated with VCO
(2009-10-01)
Wang, Wen-Chieh
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A low-power K-band CMOS current-mode up-conversion mixer is proposed. The proposed mixer is realized using four analog current-squaring circuits. This current-mode up-conversion mixer is fabricated in 0.13-mu m 1P8M triple-well CMOS process, and has the measured power conversion gain of -5 dB. The fabricated CMOS up-conversion mixer dissipates only 3.1 mW from a 1-V supply voltage. The VCO can be tuned from 20.8 GHz to 22.7 GHz. Its phase noise is -108 dBc/Hz at 10-MHz offset frequency. It is shown that the proposed mixer has great potential for low-voltage and low-power CMOS transmitter front-ends in advanced nano-CMOS technologies.
Current-mode design techniques in low-voltage 24-GHz RF CMOS receiver front-end
(2009-03-01)
Wu, Chung-Yu
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Wang, Wen-Chieh
;
Shahroury, Fadi R.
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Huang, Zue-Der
;
Zhan, Hao-Jie
A new high frequency CMOS current-mode receiver front-end composed of a current-mode low noise amplifier (LNA) and a current-mode down-conversion mixer has been proposed in the frequency band of 24 GHz and fabricated in 0.13-mu m 1P8M CMOS technology. The measurement of the current-mode receiver front-end exhibits a conversion gain of 11.3 dB, a noise figure (NF) of 14.2 dB, the input-referred 1-dB compression point (P-(1) (dB)) of -13.5 dBm and the input-referred third-order intercept point (P (IIP3)) of -1 dBm. The receiver dissipates 27.8 mW where the supply of LNA is 0.8 V and the supply of mixer is 1.2 V. The power consumption of output buffer is not included. The receiver front-end occupies the active area of 1.45 x 0.72 mm(2) including testing pads. The measured results show that the proposed current-mode approach can be applied to a high-frequency receiver front-end and is capable of low-voltage applications in the advanced CMOS technologies.
Methane Exposure on the Aluminum Nitride Gate Dielectric in Pentacene-Based Organic Thin-Film Transistors
(2009)
Chou, Cheng-Wei
;
Zan, Hsiao-Wen
;
Wang, Chung-Hwa
;
Chen, Wei-Tsung
;
Tsai, Li-Shiuan
The device performance of a pentacene-based organic thin-film transistor (OTFT) fabricated on an aluminum nitride (AlN) surface can be improved by exposing AlN to a methane (CH(4)) gas before device fabrication. The mobility of the OTFT was enhanced from 0.046 to 0.924 cm(2)/V s by exposing AlN to CH(4). Its threshold voltage was reduced from -4.5 to -1.9 V. After the CH(4) exposure, the reduced surface energy of AlN was correlated with the improvement of the OTFT performance. The reduction of surface energy was correlated with the replacement of O-C=O bonds by C-O bonds and hydrocarbon (CH(x)) on the AlN surface. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3182823] All rights reserved.
Surface defect engineering: gigantic enhancement in the optical and gas detection ability of metal oxide sensor
(2016-01-01)
Wang, Wen-Chieh
;
Lai, Chun-Yen
;
Lin, Yu-Ting
;
Yua, Tzu-Hsuan
;
Chen, Zong-Yi
In this work, the detection ability of nanosensors can be improved extraordinarily via surface defect engineering. A kinked SnO2-X/SnO2 nanostructure was fabricated by tuning the oxygen flow, and this kinked SnO2-X/SnO2 nanostructure was used to study the mechanism of surface defect (oxygen vacancy, V-O) effects via electric measurements. For UV light sensing, the response of the SnO2-X NW device is always better than the SnO2 NW device, and is two orders higher under pure O-2 surrounding conditions. The detection mechanism can be clarified by changing the detection environment (oxygen concentration) and the UV light detection sensitivity can be improved by increasing the surface V-O density. Furthermore, the SnO2-X NW device is very sensitive to its surrounding environment due to the high surface V-O density. Hence, CO/O-2 alternate-detection was used to verify our hypothesis; the results show that the SnO2-X NW device presents great detection abilities, compared with the SnO2 NW device. The sensitivity of the SnO2-X NW device is two orders higher and the reset/response time is faster, compared with the SnO2 NW device. To verify this hypothesis, the polycrystalline structure was fabricated to prove that the detection ability of metal oxide nanosensors can be improved gigantically by increasing surface defect amounts.
The 1-V 24-GHz low-voltage low-power current-mode transmitter in 130-nm CMOS technology
(2007)
Wang, Wen-Chieh
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new high frequency CMOS current-mode upconversion mixer is proposed to realize the transmitter frontend in the frequency band of 24 GHz. The transmitter integrates with a double-balance current-mode up-conversion mixer, an IF amplifier/repeater, a differential VCO and a differential VCO buffer/repeater. The performance of the transmitter exhibits a conversion gain of 1.3 dB, the input 1-dB compression point (P-1dB) is - 22 dBm, the input intercept 3(rd)-order compression point (P-IIP3) is - 8.75 dBm, and the output intercept 3(rd)-order compression point (P-OIP3) is - 7.44 dBm. The phase noise of the differential VCO is - 117 dBc/Hz at 10-MHz offset from 26 GHz. The proposed mixer consumes only 3.89 mW from a 1-V supply. The total power dissipation of the transmitter is 15.4 mW from 1-V supply. This chip is designed in 0.13-mu m 1P8M CMOS technology and under fabrication.
The design of integrated 3-GHz to 11-GHz CMOS transmitter for full-band ultra-wideband (UWB) applications
(2008)
Wang, Wen-Chieh
;
Liao, Chang-Ping
;
Lo, Yi-Kai
;
Huang, Zue-Der
;
Shahroury, Fadi R.
The CMOS integrated 3-GHz to 11-GHz transmitter for full-band UWB applications is proposed and designed in 0.13-mu m CMOS technology. The designed UWB transmitter is integrated with a 2:1 frequency divider, a quadrature up-conversion mixer, a balanced RF amplifier, and a 3-stage cascaded poly-phase filter. The technique of inductance peaking has been adopted to achieve 14-band operation for UWB applications. The transmitter has an average conversion gain of 12.8 dB with the gain ripple of around +/- 1.4 dB among the whole frequency band. The average input 1-dB compression point (IP(-1dB)) of the 14 bands is -12.2 dBm and the average output 1-dB compression point (OP-(1dB)) of the 14 bands is -0.4 dBm. The transmitter dissipates the power of 53.1 mW from the supply 2 voltage of 1.2 V and occupies the chip area of 1930X1635 mu m(2). This chip is designed in 0.13-mu m 1P8M CMOS technology and under fabrication.