Browsing by Author "Wang, Y. L."

Now showing 1 - 3 of 3

Copper voids improvement for the copper dual damascene interconnection process
(2008-02-01)
Wang, T. C.
;
Wang, Y. L.
;
Hsieh, T. E.
;
Chang, S. C.
;
Cheng, Y. L.
The mechanism of copper (Cu) voids formation from electro-chemical plating (ECP) followed by Cu chemical mechanical polishing (CMP) are studied in Cu dual-damascene interconnection. The formation of Cu voids at metal lines is the main problem that causes not only the failure of via-induced metal-island corrosion but also yield loss. The galvanic theory and Cu lifting mechanism are proposed to explain the dependence of Cu-void performance on the Cu grain size and the benzotriazole (BTA, C6H5N3) flow rates. In the integration process of Cu interconnects, it is found that the smaller Cu grain size in ECP conditions and less BTA flow rate in CMP processes cannot only reduce the number of Cu voids but also improve the water yield. (c) 2007 Elsevier Ltd. All rights reserved.
Effect of layout on electromigration characteristics in copper dual damascene interconnects
(2014-10-05)
Cheng, Y. L.
;
Chang, Y. M.
;
Leu, Jihperng
;
Bo, T. C.
;
Wang, Y. L.
This study demonstrates that the electromigration (EM) behavior of dual damascene Cu lines is strongly affected by the layout which surrounded the tested EM lines, especially for Cu line below 0.10 mu m used for 40 nm or below technologies. The Cu EM lifetime declines as the number of local dummy lines increase, and the global dummy line density increases with the width of the Cu line below 0.063 mu m. This work presents mechanisms of layout effects that explain the EM characteristics and can be exploited to improve the layout effect. Therefore, not only the stressed Cu line structures, but also the surrounding layouts must to be considered in assessing EM reliability of a real IC circuit in 40 nm or below technology. (C) 2014 Elsevier B.V. All rights reserved.
Relaxation-free strained SiGe with super anneal for 32nm high performance PMOS and beyond
(2006)
Yu, Ming H.
;
Li, J. H.
;
Lin, H. H.
;
Chen, C. H.
;
Ku, K. C.
The interaction of epitaxially strained SiGe and super annealing or millisecond anneal in high performance PFET fabrication was, for the first time, systematically investigated. When super annealing was applied, the quality of SiGe/Si interface, affected by subsequent ion implantation and post-SiGe thermal treatment, played an important role in SiGe strain relaxation incurring channel stress loss and defect injection to Si substrate resulting in high junction leakage. Defect injection mechanism was proposed to explain the defect formation in Si substrate. The new processing scheme, which preserved SiGe as relaxation-free and avoided defect injection, was developed and for 32nm technology. The device performance gain with 10% Id,sat increment resulting from fully strained SiGe was achieved.