Browsing by Author "Wang, Yi-Ming"

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An Efficient Hamiltonian-Cycle Power-Switch Routing for MTCMOS Designs
(2012)
Wang, Yi-Ming
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Chen, Shi-Hao
;
Chao, Mango C. -T.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Multi-threshold CMOS (MTCMOS) is currently the most popular methodology in industry for implementing a power gating design, which can effectively reduce the leakage power by turning off inactive circuit domains. However, large peak current may be consumed in a power-gated domain during its sleep-to-active mode transition. As a result, major IC foundries recommend turning on power switches one by one to reduce the peak current during the mode transition, which requires a Hamiltonian-cycle routing to serially connect all the power switches. In this paper, we propose an efficient power-switch routing framework, which can effectively and efficiently find a feasible Hamiltonian-cycle routing among power switches without violating the Manhattan distance constraint between any two power switches while handling the irregular placement of the power switches resulting from the hard macros. The proposed framework is compliant to commercial APR tools and has been used in a major design-service company for taping out complex MTCMOS designs.
Power-Switch Routing for Reducing Dynamic IR Drop in Multi-Domain MTCMOS Designs
(2014-01-01)
Wang, Yi-Ming
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Chao, Mango C. -T.
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Chen, Shi-Hao
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Li, Hung-Chun
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電子工程學系及電子研究所
This paper presents a switch-routing framework which can generate a feasible Hamiltonian-path switch routing while minimizing the dynamic IR drop of a targeted fragile active domain with an analytical model. The accuracy of the analytical model and the effectiveness of the proposed framework are validated through an advanced multi-domain mobile-phone MTCMOS design.
Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators
(2016-05)
Mu, Szu-Pang
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Chao, Mango C. -T.
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Chen, Shi-Hao
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Wang, Yi-Ming
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電子工程學系及電子研究所
This paper presents a model-fitting framework to correlate the on-chip measured ring-oscillator counts to the chip\'s maximum operating speed. This learned model can be included in an auto test equipment (ATE) software to predict the chip speed for speed binning. Such a speed-binning method can avoid the use of applying any functional test and, hence, result in a third-order test time reduction with a limited portion of chips placed into a slower bin compared with the conventional functional-test binning. This paper further presents a novel builtin self-speed-binning system, which embeds the learned chip-speed model with a built-in circuit such that the chip speed can be directly calculated on-chip without going through any offline ATE software, achieving a fourth-order test-time reduction compared with the conventional speed binning. The experiments were conducted based on 360 test chips of a 28-nm, 0.9 V, 1.6-GHz mobile-application system-on-chip.
Statistical Methodology to Identify Optimal Placement of On-Chip Process Monitors for Predicting Fmax
(2016)
Mu, Szu-Pang
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Chang, Wen-Hsiang
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Chao, Mango C. -T.
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Wang, Yi-Ming
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Chang, Ming-Tung
In previous literatures, many approaches use ring oscillators or other process monitors to correlate the chip\'s maximum operating frequency (F-max). But none of them focus on the placement of these on-chip process monitors (OPMs) on a chip. The placement will greatly influence the accuracy of a prediction model. In this paper, we first propose a simulation, framework to sample a chip\'s F-max and it\'s OPM result, These samples are used to develop our methodology of OPM placement and to verify the effectiveness of an OPM placement. Then, a model-fitting framework is presented to correlate the OPMs\' result to chip\'s F-max. Finally, we propose a methodology to idenify optimal placement of OPM for predicting F-max. The experiments demonstrate the effectiveness of our methodology in both simulation and silicon data.
Testing Methods for Detecting Stuck-open Power Switches in Coarse-Grain MTCMOS Designs
(2010)
Mu, Szu-Pang
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Wang, Yi-Ming
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Yang, Hao-Yu
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Chao, Mango C. -T.
;
Chen, Shi-Hao
Coarse-grain multi-threshold CMOS (MTCMOS) is an effective power-gating technique to reduce IC's leakage power consumption by turning off idle devices with MTCMOS power switches. In this paper, we study the usage of coarse-grain MTCMOS power switches for both logic circuits and SRAMs, and then propose corresponding methods of testing stuck-open power switches for each of them. For logic circuits, a specialized ATPG framework is proposed to generate a longest possible robust test while creating as many effective transitions in the switch-centered region as possible. For SRAMs, a novel test algorithm is proposed to exercise the worst-case power consumption and performance when stuck-open power switches exist. The experimental results based on an industrial MTCMOS technology demonstrate the advantage of our proposed testing methods on detecting stuck-open power switches for both logic circuits and SRAMs, when compared to conventional testing methods.