Browsing by Author "Wang, Yu-Jiu"

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A 60 GHz 19.6 dBm Power Amplifier With 18.3% PAE in 40 nm CMOS
(2015-02-01)
Tseng, Chien-Wei
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Wang, Yu-Jiu
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This letter reports a fully integrated 60 GHz power amplifier (PA) implemented in TSMC 40 nm CMOS technology. This PA is based on a three-stage two-way differential topology with an output transformer-based power combining network. This topology improves layout symmetry and mitigates parasitic effects between different signal paths to increase overall efficiency. The use of parasitic coupling capacitors inside a vertically-coupled transformer can increase impedance transformation ratio. This PA achieves 20.3 dB power gain, 19.6 dBm output power with 18.3% peak PAE, and 12 GHz bandwidth.
A Continuous-Wave THz Imaging System
(2013)
Pei, Ting-Hang
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Huang, Yang-Tung
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Wang, Yu-Jiu
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Chen, Wei-Zen
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Kuo, Chien-Nan
We develop a continuous wave terehertz (THz) imaging system operating at 288 GHz. This imaging system simply consitutes three parts including the source, two optical lenses, and the detector. The entire size is smaller than the tranditional pulsed THz imaging system. In this developed system, the THz wave is generated by a horn attenna which concentrates the wave in an azimuth angle of 3 degrees similar to 5 degrees. The source originates from a singnal generator, and then the frequency increases to 288 GHz after passing through an 8X multiplier. Next, THz wave is focused by a THz lens on the test sample. By controling the sample position in the x-z plane, we can scan it pixel-by-pixel in which each step along the x- or z- axes is 0.1 mm. After penetrating the test sample, another lens collects the transmitted THz wave and focuses them into the thermal detector. This detector can disply the collected THz power. Finally, by drawing the detected power of each pixel, a transmitted-intensity figure for all pixels is obtained. The resolution of this THz imaging system is about 1 similar to 2 mm at present. We have measured human molar tooth and obtained its transmitted figures. Besides, we also develop a technology to adjust the positions of the source and detector by a system containing one laser, one beamsplitter, and two mirrors. The relative positions between the source and detector is very important. The input of the source and the output of the detector are small so that they have to aim at each other very accurately in order to collect maximum transmitted power in the detector.
A Fully-Integrated Ka-Band 4TX/4RX Phased-Array Transceiver IC in 65nm CMOS
(2016)
Chu, Ching-Yun
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Tseng, Shao-Ting
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Gao, Jing-Zhi
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Chen, Yuan-Pu
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Chang, Yu-Chen
This paper presents a fully-integrated Ka-band 4RX/4TX phased-array transceiver IC. The four transceiver channels are synchronized by an I/Q standing wave oscillator (SWO). Their signal phases are shifted by hybrid analog IF and LO phase interpolators, and can be controlled digitally and independently. The SWO further composes an on-chip PLL, and is locked to a 1.09 GHz off-chip global reference to scale to a large array at board level. Each receiver channel achieves 66 dB maximum conversion gain and 4.4 dB minimum noise figure. Each transmitter channel achieves 18 dBm maximum output power. The chip is mounted on a high-frequency laminate, inside which embedded cables connect its RF pads to Vivaldi antennas also inside the same PCB. With the PCB, each channel achieves 360 degrees phase shifting capability under a maximum calibrated 3.7 degrees phase errors. The PCB module presents successful beam steering with 23 degrees measured four-channel 3-dB beamwidth. This chip consumes a peak 5 W power at transmit mode, and is fabricated in TSMC 65nm CMOS technology with a 4 x 2.5 mm(2) chip area.
A Ka-Band Scalable Hybrid Phased Array Based on Four-Element ICs
(2020-01-01)
Chu, Ching-Yun
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Chen, Yuan-Pu
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Gao, Jing-Zhi
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Ke, Cheng-Yung
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Chen, Yu-Wei
In this article, a scalable hybrid phased-array system is presented through synchronization, analog complex weighting, and digital beamforming of numerous fully integrated Ka-band four-receiver (RX)/four-transmitter (TX) phased-array transceiver integrated circuits (ICs). A 1.09-GHz clock synchronizes the local oscillator (LO) and a 50-MHz clock synchronizes analog-to-digital (A/D)/digital-to-analog (D/A) converters for all array elements. Phase shifting is first accomplished in the analog domain using optimal intermediate frequency (IF)/LO complex weighting and signal summing in the 4RX/4TX IC to reduce the number of signals by a factor of four, followed by A/D sampling and digital beamforming in field-programmable gate arrays (FPGAs) and central processing units (CPUs). Phase-shifting properties, programmable gain variations, and antenna patterns of each RTX channel are measured and tabulated to calculate the optimal channel weights. The long-term phase stability is enhanced through temperature control by monitoring all ICs' temperatures in real time and adaptively adjusting the duty cycle of the TX mode of each IC to limit instantaneous temperature variations to +/- 0.5 degrees C over each calibration session. This reduces random phase errors from 13.3 degrees to 4.8 degrees in the TX mode. After each Vivaldi antenna is located on a 2-D rectangular grid, an 8 x 4 subarray module with synchronized digital output is demonstrated. With the boresight pointing along the x-axis, the eight-element dimension pointing along the y-axis, and the four-element dimension pointing along the z-axis, this subarray steers radiation patterns with the E-field polarized to the y-axis between +/- 40 degrees in both azimuth and elevation with 13.4 degrees and 26.4 degrees measured 3-dB beamwidths, respectively.
A Millimeter-Wave In-Phase Gate-Boosting Rectifier
(2014-11-01)
Wang, Yu-Jiu
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Liao, I-No
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Tsai, Chao-Han
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Pakasiri, Chatrpol
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電子工程學系及電子研究所
This paper introduces a new class of RF-to-dc rectifiers called the in-phase gate-boosting rectifier (IGR). An IGR utilizes an in-phase passive voltage multiplier (IPVM) to boost in-phase swing from the driving swing. This design simultaneously reduces the effective threshold voltage, forward resistance, and the reverse leakage current of the rectifying transistor. As a consequence, the sensitivity and the efficiency of a high-frequency rectifier can be improved. Furthermore, a C-G-loaded IPVM presents low input conductance and is shunted with the drains/sources of the rectifying transistors. This makes the realization of the input matching network between the IGR core and the antenna easier, and achieves a higher voltage swing at the input terminals of the IGR core. The criteria, properties, and relating proofs of the IPVM are also discussed. A differential seven-stage millimeter-wave IGR is implemented in a 65-nm RF CMOS process. In this design, an interleaving internal threshold cancellation bias scheme is also introduced to further suppress the power consumption due to biasing circuitry without increasing the layout area. The implemented integrated circuit achieves a state-of-the-art -7-dBm sensitivity with 20% peak efficiency at 53 GHz and a bandwidth of 10 GHz from 46 to 56 GHz.
A PVT-Independent Constant-G(m) Bias Technique Based on Analog Computation
(2014-10-01)
Chu, Ching-Yun
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Wang, Yu-Jiu
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This brief presents a new process, voltage, and temperature (PVT)-independent constant-G(m) bias technique for any I-out(V-in)-monotonic convex (or concave) transconductors. In this brief, the conventional constant-g(m) biasing is formulated into an analog computation process that calculates the constant-G(m) bias voltage V-0 from an input current. An analog computer measures the effective G(m) from two matched transconductors and converges it to the inverse of a precision resistance by adjusting V-0. Through this, a well-defined large-signal constant-G(m) bias voltage can be found. The proposed technique eliminates the power-law or exponential-law assumptions on the I-out(V-in) characteristics in a conventional design. An interpolation calculation follows to find the optimal small-signal constant-g(m) bias voltage V-out. The fundamental limitations of the proposed technique are the required monotonicity and convexity (or concavity) of the transconductor\'s I-out(V-in). Error sources include mismatches of paired devices and the input offset voltage and open-loop gain of the operation amplifier (OpAmp). These errors are analyzed in detail in this brief. Biasing circuits based on different transistor types are designed using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS process. Computer simulations show that the proposed biasing circuitry can achieve +/- 0.22% g(m) variations from -60 degrees C to 130 degrees C.
A Single-Port Duplex RF Front-End for X-Band Single-Antenna FMCW Radar in 65nm CMOS
(2017-01-01)
Kao, Yu-Hsien
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Chou, Hao-Chung
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Peng, Chun-Chieh
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Wang, Yu-Jiu
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Su, Borching
A Wideband 20 mW UHF Rectifier in CMOS
(2015-06-01)
Tsai, Chao-Han
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Liao, I. -No
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Pakasiri, Chatrpol
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Pan, Hsin-Cheng
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Wang, Yu-Jiu
This letter presents the first CMOSFET RF-to-DC Rectifier IC which delivers more than 10 mW dc power at GHz frequency. This IC utilizes the single-ended In-phase Gate-boosting Rectifier (IGR) architecture, and its In-Phase Voltage Multiplier (IPVM) is derived from a lambda/2 transmission line to boost in-phase V-GS from the driving V-DS. This simultaneously reduces the effective threshold voltage, forward resistance, and reverse leakage current of the rectifying transistors. To improve an IGR\'s performance, both RF source-pull and dc load-pull are carried out to find the optimal performance. The UHF IGR is implemented using thick-gate-oxide I/O transistors with 0.28 mu m minimum gate length in TSMC 65 nm CMOS process. The implemented IC achieves a 20 mW output dc power with 31.8% peak efficiency at 900 MHz with 200 MHz 1 dB bandwidth.
An X-band Waveguide Jig for Pre-screening Testing of Fully-integrated Elementary Phased-array Transceiver Antenna-in-package
(2018-01-01)
Chang, Li-Han
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Wang, Chien Cheng
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Wu, Yue Ming
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Chu, Ta-Shun
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Wang, Yu-Jiu
A large 9-10 GHz tile-based scalable phased-array system (over 128 elements) is built by flip-chip bonding of elementary antenna-in-package (AiP) modules on a large interposer PCB. Each module has a top radiating surface and a bottom BGA bonding surface. Due to the strict spacing requirement of a phased-array system, rework of any failed modules from the interposer PCB is prone to create more damages to the system and is prohibited. It is necessary to have a reliable and Automatic Test Equipment (ATE)-compatible test procedures to pre-screen qualified elementary modules for bonding. However, conventional ATE-compatible test jig designs can neither receive radiation signals from antenna nor feed test signals into the antenna. In this paper, a waveguide jig for AiP pre-screening is proposed. This jig system consists of a WR-90 adapter, a horn antenna, a Torlon cap and socket with POGO pins, and a PCB to interface with ATE. To test AiP transmitter, controls and test signals are provided through PCB connectors, with radiation signals collected from the WR-90 adaptor. To test the AiP receiver, radiation signals are feeding through the WR-90 adaptor, and the receiver output signals are collected from the PCB connectors. To calibrate waveguide jig return loss, a set of AiP SOL modules are used to remove PCB and test fixture loss from the overall system loss. The waveguide jig achieves a flat simulated -2.4 dB from AiP antenna port to waveguide port from 8 to 12 GHz. This waveguide jig provides a fast and reliable approach to select qualified AiP for phased array system assemblies, and the final system-level over-the-air testing.