Browsing by Author "Watanabe, Hiroshi"

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A Tight Binding Method Study of Optimized Si-SiO(2) System
(2010-11-01)
Watanabe, Hiroshi
;
Kawabata, Kenji
;
Ichikawa, Takashi
;
電子工程學系及電子研究所
;
友訊交大聯合研發中心
A mixed method of molecular dynamics and tight binding is applied to a Si-cluster surrounded by SiO(2) in order to study an influence of interfacial states on the band structure of the Si cluster. As a result, it is found that intrinsic interfacial states invade the band gaps of Si and SiO(2) from the conduction band, which may suggest that the Si dot surrounded by SiO(2) sounds metallic due to the interfacial states. This feature occurs while the size of the Si dot is less than at least 4 nm.
A Tight Binding Method Study of Optimized Si-SiO2 System
(2010-11-01)
Watanabe, Hiroshi
;
Kawabata, Kenji
;
Ichikawa, Takashi
;
電子工程學系及電子研究所
;
電子與資訊研究中心
A mixed method of molecular dynamics and tight binding is applied to a Si-cluster surrounded by SiO2 in order to study an influence of interfacial states on the band structure of the Si cluster. As a result, it is found that intrinsic interfacial states invade the band gaps of Si and SiO2 from the conduction band, which may suggest that the Si dot surrounded by SiO2 sounds metallic due to the interfacial states. This feature occurs while the size of the Si dot is less than at least 4 nm.
Experimental Study of 1/f(1+alpha) Noise in Transient Leakage Current of Metal-Insulator-Metal With Stacked High-k Polycrystalline Films
(2020-06-01)
Lin, Hsin-Jyun
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Akiyama, Koji
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Hirota, Yoshihiro
;
Akasaka, Yasushi
;
Nakamura, Genji
We have observed and analyzed the 1/f(1+alpha) noise in transient leakage current through a metal-insulator-metal stacked high-k capacitor of TiN-ZrO2-TiO2-TiN. The ZrO2 and TiO2 films, formed by atomic layer deposition, are polycrystalline and show geometrical variety at interfaces (i.e., grain boundaries). Two types of transient leakage current are observed: 1) the monotonically decreasing component with power law dependence and 2) the uneven component having power law dependence. To analyze the uneven component in time domain, we assumed that the power law decay occurs due to a gradual change in the redistribution of electrons between interfaces of ZrO2-TiN and ZrO2-TiO2. The frequency-domain analysis shows that the 1/f(1+alpha) noise comes from the transient leakage of direct tunneling and trap-assisted tunneling (alpha > 0). In particular, the noise in the uneven component, the random telegraph noise part (alpha similar to 1), relates to local trap states in a grain boundary affected by phonon scattering. In addition, the analytical method we developed in this article shows an excellent agreement with variousmeasurements of the transient gate leakage current.
Integrated Batteryless Electron Timer
(2011-03-01)
Watanabe, Hiroshi
;
Ushijima, Tomomi
;
Hagiwara, Norio
;
Okada, Chiomi
;
Tanabe, Takeshi
From the viewpoint of information security, the semiconductor timing devices are reviewed, and a promising cell with floating gate (FG) is proposed as an integrated batteryless electron timer. The first issue is the difficulty in the timing precision, which is related to the trap-detrapping phenomena in the tunnel oxide between the FG and the silicon surface. The basic idea to resolve this issue is to monitor the trap-free cells among a plurality of prepared cells. The integrated batteryless electron timer is composed of a plurality of single-polysilicon-type solid-state aging devices that are connected in parallel. The first sample is fabricated in a standard complementary metal-oxide-semiconductor process, and the measurements clearly exhibit the first evidence that we succeeded to remove the trap-detrapping-related fluctuation in the ticking operation. The resultant secondary issues on the precision, i.e., the manufacturing fluctuation (subjecting to the central-limit theorem) and the temperature dependence, are also briefly discussed.
Localized Tunneling Phenomena of Nanometer Scaled High-K Gate-Stack
(2017-08-01)
Lin, Po-Jui Jerry
;
Lee, Che-An Andy
;
Yao, Chih-Wei Kira
;
Lin, Hsin-Jyun Vincent
;
Watanabe, Hiroshi
The 3-D simulator, which is capable of sensing potential change due to single electron's movement via a local trap inside the high-K gate-stacking block, is developed. Then, we carefully investigate how the electron's movement effects on the reliabilities of high-K gate-stack far beyond 10-nm generations. The simulation result shows that the potential change caused by a single electron's charge is about a few hundered millivolts inside the high-K gate-stacking block. By this result, random telegraph noise (RTN) and trap-assisted tunneling (TAT) are carefully investigated with respect to various applied biases, interface suboxide layer thicknesses, and the dielectric constant of high-K dielectrics (K). We also take into account the Coulomb blockade of a local trap, and then obtain several phase diagrams for distinguishing RTN and TAT under various conditions. It is then found that K = 30 can most effectively suppress the gate leakage current.
Monte Carlo Simulation of Nanowires Array Biosensor With AC Electroosmosis
(2018-05-01)
Lee, Che-An
;
Teramoto, Akinobu
;
Watanabe, Hiroshi
;
電機工程學系
;
Department of Electrical and Computer Engineering
Critically important for electronic biosensing is to reduce detection time that is necessary to sense the capture of biomolecules. The essential factors to study the detection time are the number of captured biomolecules per unit time and the sensitivity of capturing biomolecules. In this paper, we numerically study how ac electroosmosis (ACEO) improves the performance of biosensor unit comprising 400 nanowires by using a Monte Carlo simulation. Note that the number of captured biomolecules per unit time hardly increases if a depleted fluid layer hides the biosensor unit from biomolecules in electrolyte. However, the Monte Carlo simulation tells us that ACEO removes the depleted fluid layer by circulating the electrolyte. This improves the capture efficiency by 4.4 times and the detection speed by 24.8 times. Furthermore, we discuss the scaling effect of nanowires on the sensitivity. As a result, we can more improve the sensitivity if we bury nanowires in a planar oxide layer than wrapping it by an oxide film.
Monte Carlo simulation of random dopant fluctuation in C-V characteristics using image charge model and adequately determined length scale
(2019-09-01)
Chih-Wei, Yao
;
Sano, Nobuyuki
;
Watanabe, Hiroshi
;
電機工程學系
;
電信工程研究所
In recent years, it has been under discussion how the distribution of discrete dopant ions affects the performance of electron devices. In particular, dopant ions near the interface may not be surrounded by a sufficient number of carriers to achieve full screening. In addition, the screening effect is modeled assuming equilibrium, which cannot be validated. Therefore, the device modeling of the screening effect must be refined to cover the entire range of applied voltages. In the present work, we adequately define the length scale covering the entire voltage region in the capacitancevoltage (C-V) characteristics. Furthermore, we propose an image charge model for residual long-range potential of dopant ions near the interface. The Monte Carlo simulation of random dopant fluctuation in the C-V characteristics of 100 samples of MOS capacitors demonstrates that the main contributor to random dopant fluctuation is the location fluctuation of discrete dopant ions. (C) 2019 The Japan Society of Applied Physics.
Monte-Carlo Simulation of Biomolecules' Fluid-Dynamics in Electrolyte Facing Nanowires Biosensor
(2017-01-01)
Lee, Che-An
;
Teramoto, Akinobu
;
Watanabe, Hiroshi
;
電機工程學系
;
Department of Electrical and Computer Engineering
3D Monte-Carlo simulation of biomolecules' fluid dynamics in a specially designed biosensor comprising plurality of nanowires is presented. It is found that an AC external field can substantially improve the performance of the biosensor; e.g., the capture efficiency by 4.5-times and the detection speed by 24.8-times.
Nano-meter Scaled Gate Area High-K Dielectrics with Trap-Assisted Tunneling and Random Telegraph Noise
(2014-01-01)
Lin, Po-Jui Jerry
;
Lee, Zhe-An Andy
;
Yao, Chih-Wei Kira
;
Lin, Hsin-Jyun Vincent
;
Watanabe, Hiroshi
If the trap density is 10(12)cm(-2), then there are only one trap in 10nm x 10nm on average. Accordingly, three-dimensional simulation that is sensitive to the movement of sole electron is indispensable for carefully investigating the reliability issues related to local traps in future nano-electron devices. As a demonstration, we investigate Random Telegraph Noise (RTN) and Trap-Assisted Tunneling (TAT) at the same moment in 5nmx5nm gate area high-K dielectrics (EOT=0.8nm to 0.47nm). The simulation is carried out with respect to various gate biases, physical thickness of high-K, interlayer suboxide thickness, and dielectric constant of high-K. It is suggested that thinner suboxide and higher permittivity can suppress the increase of the leakage current which is caused by TAT.
Numerical Study of Very Small Floating Islands
(2014-04-01)
Watanabe, Hiroshi
;
Yao, Kira (Chih-Wei)
;
Lin, Jerry (Po-Jui)
;
交大名義發表
;
電機資訊學士班
The electrical property of very small floating island whose diameter is less than the de Broglie length is numerically investigated without fitting parameters. In general, it is difficult to well define the capacitance of very small floating islands. In this paper, instead of using the capacitance of islands, the kicking algorithm is applied for simulating the single-electron phenomena of spherical islands (the diameter: O = 0.6, 4, and 6 nm). As a result, the self-potentials of islands are successfully obtained within the precision equivalent to the movement of the sole electron with regard to given gate voltages. In addition, the transient simulation is demonstrated using the dwell time during which an electron is waiting for the next tunneling. The Coulomb blockade is successfully simulated without using the capacitance of very small floating islands. It is also found that trap-assisted tunneling is prohibited by Coulomb blockade at low electric field and can occur at high electric field.
Physics of Discrete Impurities under the Framework of Device Simulations for Nanostructure Devices
(2018-12-01)
Sano, Nobuyuki
;
Yoshida, Katsuhisa
;
Yao, Chih-Wei
;
Watanabe, Hiroshi
;
電機工程學系
Localized impurities doped in the semiconductor substrate of nanostructure devices play an essential role in understanding and resolving transport and variability issues in device characteristics. Modeling discrete impurities under the framework of device simulations is, therefore, an urgent need for reliable prediction of device performance via device simulations. In the present paper, we discuss the details of the physics associated with localized impurities in nanostructure devices, which are inherent, yet nontrivial, to any device simulation schemes: The physical interpretation and the role of electrostatic Coulomb potential in device simulations are clarified. We then show that a naive introduction of localized impurities into the Poisson equation leads to a logical inconsistency within the framework of the drift-diffusion simulations. We describe a systematic methodology for how to treat the Coulomb potential consistently with both the Poisson and current-continuity (transport) equations. The methodology is extended to the case of nanostructure devices so that the effects of the interface between different materials are taken into account.
Quantitative Discussion on Electron-hole Universal Tunnel Mass in Ultrathin Dielectric of Oxide and Oxide-Nitride
(2011)
Watanabe, Hiroshi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
MOS and MIS capacitor has been extensively studied in past several decades by many authors. It has been expected to reveal how basic physics relate electron device operation. In this structure, several physical phenomena co-work and then exhibit the electrical properties measured in IV- and CV-characteristics. On the other hand, the conventional models were established separately for the inversion layer (positive gate voltage), the depletion region (negative-low gate voltage), and the accumulation region (negative-high gate voltage). In addition, actual MOS/MIS samples have interfacial transition layer where physical properties are gradually changed from Si to oxide or other dielectric, the varying composition ratio of molecules and local traps owing to atomistic dangling bonds through dielectric layer. What will happen if we self-consistently unify all the physical models that are separately developed?
Statistical Simulation of Metal-Gate Work-function Fluctuation in High-kappa/Metal-Gate Devices
(2010)
Yu, Chia-Hui
;
Han, Ming-Hung
;
Cheng, Hui-Wen
;
Su, Zhong-Cheng
;
Li, Yiming
In this work, we statistically examine the emerging high-kappa / metal gate work-function fluctuation (WKF) induced threshold voltage (V(th)) fluctuations in 16-nm-gate MOSFET devices. Our Monte-Carlo model extensively evaluates the impact of WKF for different technology node, metal grain size, and gate material. This model provides us to identify suitable materials and fabrication processes that can significantly reduce the impact of Vth fluctuation owing to WKF. First, four kinds of gate material are examined and TiN possesses the smallest Vth fluctuation. For fabrication process, a fast deposition of metal at lower temperature prevents the metal grain not to grow to large size result in a smaller variation. In addition, an idea of modeling multilayer metal gate WKF is also presented and discussed, in which the first layer plays the most important role, compared with other layers, for the fluctuation suppression.
Three-dimensional device simulation of random telegraph noise spectroscopy with Coulomb energy variation of the trap in high-k gate oxide
(2018-12-01)
Lin, Po-Jui
;
Su, Chong-Zih
;
Yao, Chih-Wei
;
Watanabe, Hiroshi
;
電機工程學系
The random telegraph noise (RTN) time constants, capture (T-C) and emission (T-e) times, have been extensively used to identify the trap position in the gate oxide by comparing the measured T-C-over-T-e ratio with the Shockley-Read-Hall (SRH) statistics. However, various factors have been shown to affect the accuracy of the extracted trap depth from the SRH-type models, such as three-dimensional (3D) device electrostatics, atomistic doping, metal gate granularity, and Coulomb energy variation (CEV) of the trap. Focusing on CEV in this work, we assume the trap in gate oxide can be regarded as a floating island and then numerically studied the CEV of the trap with 3D drift-diffusion simulation. Analyzing the simulation data, the extracted trap depth without considering CEV in the SRH statistics are quantitatively compared with the data involved CEV. (C) 2018 The Japan Society of Applied Physics
Transient Device Simulation of Floating Gate Nonvolatile Memory Cell With a Local Trap
(2010-08-01)
Watanabe, Hiroshi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The single-electron general-purpose device simulator is improved to carry out a wide-range transient analysis from 1 ps to 10 years. We apply this simulator to a floating gate (FG) nonvolatile memory cell in order to simulate a degradation mode of data retention owing to the direct tunneling enhanced by the fixed charge stored by a local trap in an interpoly dielectric. The scaling impact of ideal high-K interpoly dielectric FG nonvolatile memory cell is also investigated.
Universal Tunnel Mass and Charge Trapping in [(SiO(2))(1-x)(Si(3)N(4))(x)](1-y)Si(y) Film
(2010-05-01)
Watanabe, Hiroshi
;
Matsushita, Daisuke
;
Muraoka, Kouichi
;
Kato, Koichi
;
資訊工程學系
Although the tunnel mass is indispensable to predict the gate leakage current of electron devices, it has been regarded as an adjustable parameter to fit the calculated leakage current with the measured ones. This appears useful because it enables calculation of the tunnel current while ignoring some details in advanced device modeling, even though it has veiled the intuitive nature of the modeling. More concretely, the adjustable tunnel mass pushes us to ignore the related issues that should carefully be considered. In this paper, we extract the tunnel masses for electrons and holes from an individual experiment and find that they are 0.85m(0), where m(0) is the rest electron mass, irrespective of the molecular compound ratio between Si(3)N(4) and SiO(2) and the film thickness. This suggests a convincing model for charge trapping in [(SiO(2))(1-x)(Si(3)N(4))(x)](1-y)Si(y) including interfacial transition layers. It is also found that the leakage mechanism is the direct tunneling enhanced by the trapped positive charge.
Universal Tunnel Mass and Charge Trapping in [(SiO2)(1-x)(Si3N4)(x)](1-y)Si-y Film
(2010-05-01)
Watanabe, Hiroshi
;
Matsushita, Daisuke
;
Muraoka, Kouichi
;
Kato, Koichi
;
電子工程學系及電子研究所
Although the tunnel mass is indispensable to predict the gate leakage current of electron devices, it has been regarded as an adjustable parameter to fit the calculated leakage current with the measured ones. This appears useful because it enables calculation of the tunnel current while ignoring some details in advanced device modeling, even though it has veiled the intuitive nature of the modeling. More concretely, the adjustable tunnel mass pushes us to ignore the related issues that should carefully be considered. In this paper, we extract the tunnel masses for electrons and holes from an individual experiment and find that they are 0.85m(0), where m(0) is the rest electron mass, irrespective of the molecular compound ratio between Si3N4 and SiO2 and the film thickness. This suggests a convincing model for charge trapping in [(SiO2)(1-x)(Si3N4)(x)](1-y)Si-y including interfacial transition layers. It is also found that the leakage mechanism is the direct tunneling enhanced by the trapped positive charge.