Browsing by Author "Wei, JS"

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A variable partitioning algorithm of BDD for FPGA technology mapping
(1997-10-01)
Jiang, JH
;
Jou, JY
;
Huang, JD
;
Wei, JS
;
交大名義發表
Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than the similar works of the previous approaches [1], [4].
BDD based lambda set selection in Roth-Karp decomposition for LUT architecture
(1996)
Jiang, JH
;
Jou, JY
;
Huang, JD
;
Wei, JS
;
交大名義發表
Field Programmable Gate Arrays (FPGA's) are important devices for rapid system prototyping. Roth-Karp decomposition is one of the most popular decomposition techniques for Look-Up Table (LUT)-based FPGA technology mapping. In this paper, we propose a novel algorithm based on Binary Decision Diagrams (BDD's) for selecting good lambda set variables in Roth-Karp decomposition to minimize the number of consumed configurable logic blocks (CLB's) in FPGA's. The experimental results on a set of benchmarks show that our algorithm can produce much better results than those of the previous approach [1].