Browsing by Author "Wei, Shu-Han"

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Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs
(2013-01-01)
Wei, Shu-Han
;
Lee, Yu-Min
;
Ho, Chia-Tung
;
Sun, Chih-Ting
;
Cheng, Liang-Chia
This work presents effective techniques for minimizing wiring resources and power TSVs (PTSVs) of 3-D power delivery network design under IR drop constraints. First, a 3-D power grid topology optimization is performed to generate power grid by utilizing locally uniform and globally non-uniform power grid configurations. After that, two developed power TSV planners are executed to minimize the maximum IR drop without the full-chip power-grid analysis. Finally, the above procedures are repeatedly performed with a rescue procedure to remedy the violated constraints until the designed PDN is satisfied. To further enhance the design procedure, a partition-based design flow is proposed by dividing the entire chip into tiles, and each of them is designed independently by the proposed procedure. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of partition-based strategy in the design flow is imperative.
Power Delivery Network Design for Wiring and TSV Resource Minimization in TSV-Based 3-D ICs
(2013)
Wei, Shu-Han
;
Lee, Yu-Min
;
Ho, Chia-Tung
;
Sun, Chih-Ting
;
Cheng, Liang-Chia
This work presents effective techniques for minimizing wiring resources and power TSVs (PTSVs) of 3-D power delivery network design under IR drop constraints. First, a 3-D power grid topology optimization is performed to generate power grid by utilizing locally uniform and globally non-uniform power grid configurations. After that, two developed power TSV planners are executed to minimize the maximum IR drop without the full-chip power-grid analysis. Finally, the above procedures are repeatedly performed with a rescue procedure to remedy the violated constraints until the designed PDN is satisfied. To further enhance the design procedure, a partition-based design flow is proposed by dividing the entire chip into tiles, and each of them is designed independently by the proposed procedure. The experimental results demonstrate the effectiveness of the developed methodology and indicate that the consideration of partition-based strategy in the design flow is imperative.