Browsing by Author "Wen, Chao-Kai"

Now showing 1 - 9 of 9

Bayes-Optimal Joint Channel-and-Data Estimation for Massive MIMO With Low-Precision ADCs
(2016-05-15)
Wen, Chao-Kai
;
Wang, Chang-Jen
;
Jin, Shi
;
Wong, Kai-Kit
;
Ting, Pangan
This paper considers a multiple-input multipleoutput (MIMO) receiver with very low-precision analog-to-digital convertors (ADCs) with the goal of developing massive MIMO antenna systems that require minimal cost and power. Previous studies demonstrated that the training duration should be relatively long to obtain acceptable channel state information. To address this requirement, we adopt a joint channel-and-data (JCD) estimation method based on Bayes-optimal inference. This method yields minimal mean square errors with respect to the channels and payload data. We develop a Bayes-optimal JCD estimator using a recent technique based on approximate message passing. We then present an analytical framework to study the theoretical performance of the estimator in the large-system limit. Simulation results confirm our analytical results, which allow the efficient evaluation of the performance of quantized massive MIMO systems and provide insights into effective system design.
Decentralized Expectation Consistent Signal Recovery for Phase Retrieval
(2020-01-01)
Wang, Chang-Jen
;
Wen, Chao-Kai
;
Tsai, Shang-Ho
;
Jin, Shi
;
電子工程學系及電子研究所
In this study, we present a phase retrieval solution that aims to recover signals from noisy phaseless measurements. A recently proposed scheme known as generalized expectation consistent signal recovery (GEC-SR), has shown better accuracy, speed, and robustness than many existing methods. However, sensing high-resolution images with large transform matrices presents a computational burden for GEC-SR, thereby limiting its applications to areas, such as real-time implementation. Moreover, GEC-SR does not support distributed computing, which is an important requirement to modern computing. To address these issues, we propose a novel decentralized algorithm called & x201C;deGEC-SR & x201D; by leveraging the core framework of GEC-SR. deGEC-SR exhibits excellent performance similar to GEC-SR but runs tens to hundreds of times faster than GEC-SR. We derive the theoretical state evolution for deGEC-SR and demonstrate its accuracy using numerical results. Analysis allows quick generation of performance predictions and enriches our understanding on the proposed algorithm.
Finite-Alphabet Precoding for Massive MU-MIMO With Low-Resolution DACs
(2018-07-01)
Wang, Chang-Jen
;
Wen, Chao-Kai
;
Jin, Shi
;
Tsai, Shang-Ho
;
電子工程學系及電子研究所
Massive multiuser multiple-input multiple-output (MU-MIMO) systems are expected to he the core technology in fifth-generation wireless systems because they significantly improve spectral efficiency. However, the requirement for a large number of radio frequency (RF) chains results in high hardware costs and power consumption, which obstruct the commercial deployment of massive MIMO systems. A potential solution is to use low-resolution digital-to-analog converters (DAC)/analogto-digital converters for each antenna and RF chain. However, using low-resolution DACs at the transmit side directly limits the degree of freedom of output signals and thus poses a challenge to the precoding design. In this paper, we develop efficient and universal algorithms for a downlink massive MU-MIMO system with finite-alphabet precodings. Our algorithms are developed based on the alternating direction method of multipliers (ADMM) framework. The original ADMM does not converge in a nonlinear discrete optimization problem. The primary cause of this problem is that the alternating (update) directions in ADMM on one side are biased, and those on the other side are unbiased. By making the two updates consistent in an unbiased manner, we develop two algorithms called iterative discrete estimation (IDE) and IDE2. IDE demonstrates excellent performance and IDE2 possesses a significantly low computational complexity. Compared with state-of-the-art techniques, the proposed preceding algorithms present significant advantages in performance and computational complexity.
Gridless Channel Estimation for Mixed One-Bit Antenna Array Systems
(2018-12-01)
Wang, Chang-Jen
;
Wen, Chao-Kai
;
Jin, Shi
;
Tsai, Shang-Ho
;
電子工程學系及電子研究所
A receiver architecture with low-resolution analogto-digital converters (ADCs) coupled with large antenna arrays has drawn considerable interest in the millimeter wave (mm-wave) system. Although architecture with pure one-bit ADCs has low power cost, such a system presents many challenges for synchronization, channel estimation, and power level estimation. Research has been conducted recently on the so-called mixed one-bit system, in which most antennas are equipped with one-bit ADCs, and a few have high-resolution ADCs. Despite the advantages of this system, studies on how to efficiently use high-resolution outputs to aid the one-bit system are lacking. This research considers the channel estimation problem to fill this gap and proposes a two-step channel estimator by utilizing the different features of mixed outputs. The channel gain can he extracted from high-resolution ADCs, and the channel angle can be extracted by the combination of additional one-bit ADCs. The proposed estimator leverages the sparsity feature of the channel in mm-wave. In contrast to previous works that used compressive sensing techniques, which confine the estimate to the set of grid angle points and induce estimation bias, the proposed estimator is gridless and treats the angle as a continuous parameter. The simulation results demonstrate that the proposed method yields significantly lower mean square errors than the conventional maximum likelihood estimator. In addition, this paper investigates ways to further improve the channel estimate by arranging the locations of high-resolution ADCs. Several useful observations on system design are obtained through our analysis.
Local Cyber-Physical Attack for Masking Line Outage and Topology Attack in Smart Grid
(2019-07-01)
Chung, Hwei-Ming
;
Li, Wen-Tai
;
Yuen, Chau
;
Chung, Wei-Ho
;
Zhang, Yan
Malicious attacks in the power system can eventually result in a large-scale cascade failure if not rectified in a timely manner. These attacks, which are traditionally classified into physical and cyber attacks, can be avoided by using the latest advanced detection mechanisms. However, a new threat called cyber-physical attacks jointly targets both the physical and cyber layers of the system to interfere with the operations of the power grid is more malicious than traditional attacks. In this paper, we propose a new cyber-physical attack strategy where the transmission line is first physically disconnected, the line-outage event is masked to mislead the control center into detecting this as an obvious line outage at a different position in the local area of the power system. Therefore, the topology information in the control center is interfered with as a result of our attack. We also propose a novel procedure for selecting vulnerable lines and analyze the observability of our proposed framework. Our proposed method can effectively and continuously deceive the control center into detecting fake line-outage positions, and thereby increase the chance of cascade failure because the attention is given to the fake outage. The simulation results validate the efficiency of our proposed attack strategy.
Phase Retrieval With Learning Unfolded Expectation Consistent Signal Recovery Algorithm
(2020-01-01)
Wang, Chang-Jen
;
Wen, Chao-Kai
;
Tsai, Shang-Ho
;
Jin, Shi
;
電子工程學系及電子研究所
Phase retrieval algorithms are now an important component of many modern computational imaging systems. A recently proposed scheme called generalized expectation consistent signal recovery (GEC-SR) shows better accuracy, speed, and robustness than numerous existing methods. Decentralized GEC-SR (deGEC-SR) addresses the scalability issue in high-resolution images. However, the convergence speed and stability of these algorithms heavily rely on the settings of several handcrafted tuning factors with inefficient turning process. In this work, we propose deGEC-SR-Net by unfolding the iterative deGEC-SR algorithm into a learning network architecture with trainable parameters. The parameters of deGEC-SR-Net are determined by data-driven training. Numerical results show that deGEC-SR-Net provides substantially faster convergence than deGEC-SR and exhibits superior robustness to noise and prior mis-specifications.
Reliable OFDM Receiver With Ultra-Low Resolution ADC
(2019-05-01)
Wang, Hanging
;
Shih, Wan-Ting
;
Wen, Chao-Kai
;
Jin, Shi
;
電控工程研究所
The use of low-resolution analog-to-digital converters can significantly reduce power consumption and hardware cost. However, their resulting severe nonlinear distortion makes achieving reliable data transmission challenging. For orthogonal frequency division multiplexing (OFDM) transmission, the orthogonality among subcarriers is destroyed. This invalidates conventional OFDM receivers relying heavily on this orthogonality. In this paper, we move on to quantized OFDM (Q-OFDM) prototyping implementation based on our previous achievement in optimal Q-OFDM detection. First, we propose a novel Q-OFDM channel estimator by extending the generalized Turbo (GTurbo) framework formerly applied for optimal detection. Specifically, we integrate a type of robust linear OFDM channel estimator into the original GTurbo framework, and derive its corresponding extrinsic information to guarantee its convergence. We also propose feasible schemes for automatic gain control, noise power estimation, and synchronization. Combined with the proposed inference algorithms, we develop an efficient Q-OFDM receiver architecture. Furthermore, we construct a proof-of-concept prototyping system and conduct over-the-air (OTA) experiments to examine its feasibility and reliability. This is the first work that focuses on both algorithm design and system implementation in the field of low-resolution quantization communication. The results of the numerical simulation and OTA experiment demonstrate that reliable data transmission can be achieved.
Wafer-scale single-crystal hexagonal boron nitride monolayers on Cu (111)
(2020-03-01)
Chen, Tse-An
;
Chuu, Chih-Piao
;
Tseng, Chien-Chih
;
Wen, Chao-Kai
;
Wong, H. -S. Philip
Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore's law of the number of transistors in an integrated circuit(1). One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering(2,3). Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces(4) or bulk copper foils(5). However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films(6,7). Growing single-crystal hBN on such high-symmetry surface planes as Cu (111)(5,8) is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics.
Wafer-scale single-crystal hexagonal boron nitride monolayers on Cu (111)
(1970-01-01)
Chen, Tse-An
;
Chuu, Chih-Piao
;
Tseng, Chien-Chih
;
Wen, Chao-Kai
;
Wong, H. -S. Philip
The epitaxial growth of single-crystal hexagonal boron nitride monolayers on a copper (111) thin film across a sapphire wafer suggests a route to the broad adoption of two-dimensional layered semiconductor materials in industry. Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore's law of the number of transistors in an integrated circuit(1). One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering(2,3). Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces(4) or bulk copper foils(5). However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films(6,7). Growing single-crystal hBN on such high-symmetry surface planes as Cu (111)(5,8) is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics.