Browsing by Author "Wen, Charles H-P"

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Advanced Soft-Error-Rate (SER) Estimation with Striking-Time and Multi-Cycle Effects
(2014-01-01)
Huang, Ryan H-M
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Wen, Charles H-P
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
Soft error rate (SER) has become a critical reliability issue for CMOS designs due to continuous technology scaling. However, the striking-time and multi-cycle effects have not been properly considered in SER for advanced CMOS designs. Therefore, in this paper, the striking-time and multicycle effects are formulated into the problem of SER estimation, and then a SER analysis framework is proposed, accordingly. Experimental results show that SERs on the benchmark circuits are seriously underestimated when ignoring both effects. Moreover, SERs increase more on those high-performance or low-power CMOS designs. New treatment to SER needs to be explored in the future.
Coupling-Aware Functional Timing Analysis for Tighter Bounds: How Much Margin Can We Relax?
(2017-01-01)
Lin, Jack S-Y
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Lin, Louis Y-Z
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Huang, Ryan H-M
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Wen, Charles H-P
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電機工程學系
As the manufacturing technology keeps scaling, crosstalk noise induces a greater impact on timing. Although many previous works proposed techniques like timing correlation, functional correlation and path refinement to consider crosstalk noise during static timing analysis, they often suffered from descendant problems including overly-pessimistic timing bound, bad aggressor selection and false paths. Therefore, in this paper, a coupling-aware functional timing analysis tool named CA-FTA is proposed to tame the three problems stated above and to derive a tighter timing bound for the true longest path. Experimental results show that CA-FTA averagely reduces timing bounds of those obtained from crosstalk STA (with path refinement) by 7.26% on several ISCAS'85 and ISPD-2012 benchmark circuits (in particular, by 34.6% for b19). As a result, CA-ETA successfully solves the aggressor-selection problem as well as the false-path problem and relaxes more margins when considering crosstalk noise.
FAE: Autoencoder-Based Failure Binning of RTL Designs for Verification and Debugging
(2019-01-01)
Shen, Cheng-Hsien
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Liang, Aaron C-W
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Hsu, Charles C-H
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Wen, Charles H-P
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電機工程學系
As the Register Transfer Level (RTL) designs are more complicated, debugging becomes a major bottleneck in the design process. To make debugging more efficient, failure binning aims at grouping failure traces caused by the same error source together so that designers can focus on one bug at one time. However, as there are multiple bugs in a design, behaviors exhibited by failure traces are diverse and severely confuse designers. One error source may result in different appearances subject to different activation conditions. In addition, different error sources may also exhibit similar appearances among the limited number of failure traces. In this work, we propose an autoencoder-based failure binning engine name FAE for debugging RTL designs more efficiently. The autoencoders extract meaningful representations from the sparse and high-dimensional feature space to the latent space with good properties for clustering. Superior to prior works, FAE provides confidence ranks between bins and in a bin to clearly guide designers during debugging. Experimental results show that FAE can drive bins of higher purity under an acceptable number of bins than prior works, dropping only few less-informative failures. Evaluated by three common metrics for clustering, FAE also achieves averagely 13.1% improvement in purity, 25.0% improvement in NMI and 18.2% improvement in ARI, respectively. As a result, the proposed autoencoder-based engine, FAE, applies machine learning to extract useful information from diverse failure traces and is effective on failure binning with more focused debugging.
Improving Quality of Experience of Service-Chain Deployment for Multiple Users
(2018-01-01)
Wang, I-Chih
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Wen, Charles H-P
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Chao, H. Jonathan
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電機工程學系
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Department of Electrical and Computer Engineering
The fifth generation (5G) mobile communication network aims at providing high-rate, low-latency services. When a user subscribes a chain of service functions (a.k.a. service chain) from the telecom providers, a Service Level Agreement (SLA) is specified according to his requirement. Deploying service chains optimally has always been a big issue. Several previous works have presented various strategies of service-chain deployment for optimizing either latency or computational resources; however, over-optimization of latency or computational resource is not necessarily equivalent to improvement on quality of experience. Therefore, in this paper, we formally formulate this problem of optimizing quality of experience with the queuing theory and mixed-integer linear programming. In addition, we propose an efficient algorithm named "QoE-driven Service-Chain Deployment with Latency Prediction" for deploying a service chain for a user in practice. According to the experiments, our algorithm reduces >99% rejections and >99% waiting time, notably elevating the quality of experience for users.
P4-TPG: Accelerating Deterministic Parallel Test Pattern Generation by Preemptive, Proactive, and Preventive Schedulings
(2019-01-01)
Lin, Louis Y-Z
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Hsu, Charles Chia-Hao
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Wen, Charles H-P
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電機工程學系
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Department of Electrical and Computer Engineering
According to the prior research, a deterministic parallel test pattern generation (TPG) engine was realized and generated the same test pattern set the serial automatic test pattern generation does during acceleration. However, for retaining the determinism, tremendous idle time is observed when different tasks (either dependent or independent) were synchronized among threads. Therefore, a new deterministic parallel TPG engine called P4-TPG is developed and incorporates preemptive, proactive, and preventive schedulings to further save/reuse the idle time during acceleration. In P4-TPG, preemptive scheduling first modifies the thread flow and brings forward, as many latter tasks as possible, to the idle time. Next, proactive scheduling inserts prospective TPG tasks of unprocessed faults to the remaining idle time and increases the overall utilization of threads. Last, preventive scheduling dynamically skips faults incompatible with the working pattern per thread and shortens the fault list during fault compaction. The experimental results show that P4-TPG not only generates the same test pattern set as the serial TPG does but also achieves averagely 10.36x speedups, is 96.6% better than the prior research, using 12 threads on 18 benchmark circuits.
Radiation-Hardened Designs for Soft-Error-Rate Reduction by Delay-Adjustable D-Flip-Flops
(2017-01-01)
Lin, Yuwen (Dave)
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Wen, Charles H-P
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Chiueh, Herming
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電機工程學系
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Department of Electrical and Computer Engineering
For reducing soft error rate (SER) in system-level failures, this paper proposes a radiation-hardened design by Delay Adjustable D Flip-Flop (DAD-FF), which can be generally applied to sequential circuits such as shift registers. DAD-FF, modified from the Built-In Soft-Error Resilience (BISER) latch, can be easily integrated in the CAD flow and its delay can be adjusted to reject particle strikes with the maximum energy level. As a result, at the device level, DAD-FF eliminates 99.999997%(1) soft errors by heavy ions on a satellite orbiting at a height of 720 km, and shows greater reduction on SER (e.g. 1.3 x 10(10)X in the best case) than the standard DFF (STD-FF) through TCAD and SPICE simulation. Moreover, a real chip was also fabricated in a CMOS 90nm technology and performed the experiment of radiation exposure in UCL, Belgium. The laboratory measurement indicates that at the system level, the radiation-hardened design by DAD-FFs achieves 15.69X and 2.62X improvements on the overall SER, compared with those by STD-FFs and DICEs, respectively.
TVM: Tabular VM Migration for Reducing Hop Violations of Service Chains in Cloud Datacenters
(2017-01-01)
Wu, Ying-Feng
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Su, Yu-Lun
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Wen, Charles H-P
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電機工程學系
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Department of Electrical and Computer Engineering
Network Function Virtualization is a recent and significant development applied in cloud datacenters, which can help service providers manage network services more flexibly and economically than using middle-boxes. User requests may demand different numbers of services in a chain, where the related flows can be directed to different physical machines (PMs) hosting required virtual network functions (VNFs) in a designated order. Sometimes, with the limited resources in current PMs, the deployment of service chains may result in great hop counts and cause hop (latency) violations against the service level agreements (SLAs) of user requests. Therefore, we propose a dynamic service-chain management approach called Tabular VM Migration (TVM) to reduce hop violations of service chains in cloud datacenters. Different from other VM management policies, TVM considers the order of a set of VMs in a service chain and migrates key VMs which may cause hop violations onto the selected PMs. Thus, hop violations are reduced with few migrations. Simulation results indicate that TVM performs better than other common VM management policies, and reduce at most 16.68% of total number of hop violations induced by a static deployment approach (SOVWin).
Unleashing Parallelism With Minimal Test Inflation in Multi-Threaded Test Pattern Generation
(2018-01-01)
Lin, Louis Y-Z
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Wen, Charles H-P
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電機工程學系
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Department of Electrical and Computer Engineering
Shared-memory systems enable parallel computing for the automatic test pattern generation (ATPG). Although the existing techniques for parallel ATPG reach near-linear speedup, test inflation becomes a common problem in its practicality. Therefore, this paper proposes a multi-threaded test pattern generation called MT-TPG that can suppress test inflation and accelerate fault processing, simultaneously, to retain high parallelism. For suppressing test inflation, hard-fault shuffling (HFS) and concurrent-fault interruption (CFI) are involved to avoid repeated detection of the same fault among different threads. For accelerating fault processing, the potentially-droppable-fault removal (PDFR) and single-pattern parallelfault simulation (SPPFSim) collectively drop not-yet-detected faults as early as possible for shortening the overall execution time of ATPG. According to our experimental results, the HFS and CFI can successfully suppress test inflation to < 4% on 17 benchmark circuits; PDFR and SPPFSim can achieve 13.7X speedup using 16 threads on average. As a result, MT-TPG is proven effective at unleashing parallelism with minimal test inflation on shared-memory systems.