Browsing by Author "Wen, Charles H. -P"

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(DENDIST)-E-2: Dynamic and Disjoint ENDIST-based Layer-2 Routing Algorithm for Cloud Datacenters
(2012)
Liu, Gen-Hen
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Wen, Charles H. -P
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Wang, Li-Chun
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
This paper presents an improved layer-2 routing algorithm, called dynamic and disjoint edge node divided spanning tree ((DENDIST)-E-2), to overcome the issues of the single path route and unbalanced link utilization in cloud datacenters. (DENDIST)-E-2 consists of two key schemes: (1) disjoint ENDIST routing and (2) reroute by dynamic reweights. The former scheme can provide multi-path routes, thereby reducing traffic congestion. The latter scheme can balance the traffic load and improve the link utilization. Our experimental results show that the proposed scheme can enhance system throughput by 25% subject to the constraint of very short failure recovery time compared to the existing ENDIST scheme.
Process-Variation-Aware Iddq Diagnosis for Nano-Scale CMOS Designs - The First Step
(2013-01-01)
Chang, Chia-Ling (Lynn)
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Wen, Charles H. -P
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Bhadra, Jayanta
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電機工程學系
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Department of Electrical and Computer Engineering
Along with the shrinking CMOS process and rapid design scaling, both Iddq values and their variation of chips increase. As a result, the defect leakages become less significant when compared to the full-chip currents, making them more in-distinguishable for traditional Iddq diagnosis. Therefore, in this paper, a new approach called s-Iddq diagnosis is proposed for reinterpreting original data and diagnosing failing chips, intelligently. The overall flow consists of two key components, (1) s-Iddq transformation and (2) defect-syndrome matching: s-Iddq transformation first manifests defect leakages by excluding both the process-variation and design-scaling impacts. Later, defect-syndrome matching applies data mining with a pre-built library to identify types and locations of defects on the fly. Experimental results show that an average of 93.68% accuracy with a resolution of 1.75 defect suspects can be achieved on ISCAS'89 and IWLS'05 benchmark circuits using a 45nm technology, demonstrating the effectiveness of s-Iddq diagnosis.