Browsing by Author "Wen, Charles H. -P."

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A Determinate Radiation Hardened Technique for Safety-Critical CMOS Designs
(2015-04-01)
Huang, Ryan H. -M.
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Hsu, Dennis K. -H.
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Wen, Charles H. -P.
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
Soft errors have been a critical concern for reliability of advanced CMOS designs due to technology scaling. Moreover, along with the rapid growth of medical, automotive, and aerospace electronics, extremely high demand on reliability becomes the paramount concern, superior to cost and performance, on these safety-critical designs. Triple modular redundancy (TMR) is widely used to mask virtually all soft errors but typically incurs high power and area overheads. Therefore, in this paper, a determinate radiation hardened technique for safety-critical CMOS designs is proposed and consists of three hybrid strategies combining gate sizing, supply voltage (V (D D) ) scaling and threshold voltage (V (t h) ) scaling to prevent soft errors from occurring. A STA-like method that computes the required pulse width of a transient fault along the propagation path is also developed in this framework. Simulation results show that the proposed technique can effectively eliminate all soft errors on ISCAS\'85 circuits and a controller area network bus electrical control unit (CAN-bus ECU) design for automotive electronics when the deposited charges range from 35 fC to 132 fC. Furthermore, the strategy using all three techniques, simultaneously improves power and area overheads by 3.3X and 2X, respectively, compared with TMR.
Accelerating Functional Timing Analysis with Encoding Duplication Removal and Redundant State Propagation
(2017-01-01)
Wu, Denny C. -Y.
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Jhao, Pin-Ru
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Wen, Charles H. -P.
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資訊工程學系
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Department of Computer Science
Functional timing analysis (FTA) emerges for better timing closure than static timing analysis (STA) by providing the true delay of the circuit as well as its input pattern. For Satisliability(SAT)-based VIA, a search problem for circuit delay can be expressed by clauses corresponding to circuit consistency function (CCF) and timed characteristic function (TCF). In particular, the clause number tends to grow exponentially as the circuit size increases, lengthening runtime for FTA. However, when formulating TCT, numerous clauses and literals are found useless. Therefore, two key techniques are proposed: (1) Encoding Duplication Removal (EDR) for removing those literals that are previously encoded in CCF but now duplicated in TCF, and (2) Redundant State Propagation (RSP) for propagating redundant states of nodes to help prune TCF clauses. Experiments indicate that under the worst-case delay of each benchmark circuit, EDR and RSP successfully reduce averagely 49% of clauses, 65% of literals, and 52% runtime on seven benchmark circuits for FTA.
Accurate performance evaluation of VLSI designs with selected CMOS process parameters
(2018-01-01)
Chang, Chia-Ling (Lynn)
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Wen, Charles H. -P.
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電機工程學系
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Department of Electrical and Computer Engineering
As process monitors have become vital components in modern very-large-scale integration (VSLI) designs, performance targets often determine the physical implementation of such monitors. However, as various process and environmental parameters collectively affect circuit behaviour, the design of process monitors can be difficult. In addition, process parameters from device-level models may not provide sufficient resolution in circuit-level performance. Therefore, the authors propose an intelligent novel flow for selecting dominant process parameters for evaluating performance targets such as timing and leakage. The proposed flow is applied to ISCAS'85, ISCAS'89, and IWLS'05 benchmark circuits and selects the dominant parameters in 32 and 45nm complementary metal-oxide-semiconductor (CMOS) technologies. Through this flow, the authors identify the supply voltage, temperature, gate-oxide thickness, and effective gate length as the four dominant factors for timing and leakage. Experimental results show that the suggested process parameters achieve high evaluation accuracy (<3% errors in timing and <1% errors in leakage on average) in the benchmark circuits. Therefore, the proposed flow can select dominant parameters for performance targets, and the four determined factors can be used to accurately evaluate timing and leakage in 32 and 45nm CMOS technologies.
Accurate Statistical Soft Error Rate (SSER) Analysis Using A Quasi-Monte Carlo Framework With Quality Cell Models
(2010)
Kuo, Yu-Hsin
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Peng, Huan-Kai
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Wen, Charles H. -P.
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電機工程學系
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Department of Electrical and Computer Engineering
For CMOS designs in sub 90nm technologies, statistical methods are necessary to accurately estimate circuit SER considering process variations. However, due to the lack of quality statistical models, current statistical SER (SSER) frameworks have not yet achieved satisfactory accuracy. In this work, we present accurate table-based cell models, based on which a Monte Carlo SSER analysis framework is built. We further propose a heuristic to customize the use of quasirandom sequences, which successfully speeds up the convergence of simulation error and hence shortens the runtime. Experimental results show that this framework is capable of more precisely estimating circuit SSERs with reasonable speed.
Aging-aware Statistical Soft-Error-Rate Analysis for Nano-Scaled CMOS Designs
(2013-01-01)
Lin, Cosette Y. H.
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Huang, Ryan H. -M.
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Wen, Charles H. -P.
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Chang, Austin C. -C.
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電機工程學系
Aging and soft errors have become the two most critical reliability issues for nano-scaled CMOS designs. In this paper, the aging effect due to negative bias temperature instability (NBTI) is first analyzed on cells using a 45nm CMOS technology for soft errors. Second, an accurate statistical soft-error-rate (SSER) framework is built and incorporates the aging-aware cell models. As a result, two findings are discovered: (1) PMOS-induced transient faults, comparing to NMOS-induced ones, have more variation in pulse widths since PMOS is more susceptible to NBTI; (2) NBTI together with process variation, induces more soft errors (similar to 19%) and thus needs to be considered, simultaneously, during circuit analysis. Experimental result shows that our SSER framework considering both process variation and aging is efficient (with multiple-order speedups) and achieves high accuracy (with <3% errors) when compared with Monte-Carlo SPICE simulation.
Aging-aware Statistical Soft-Error-Rate Analysis for Nano-Scaled CMOS Designs
(2013)
Lin, Cosette Y. H.
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Huang, Ryan H. -M.
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Wen, Charles H. -P.
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Chang, Austin C. -C.
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電機資訊學士班
Aging and soft errors have become the two most critical reliability issues for nano-scaled CMOS designs. In this paper, the aging effect due to negative bias temperature instability (NBTI) is first analyzed on cells using a 45nm CMOS technology for soft errors. Second, an accurate statistical soft-error-rate (SSER) framework is built and incorporates the aging-aware cell models. As a result, two findings are discovered: (1) PMOS-induced transient faults, comparing to NMOS-induced ones, have more variation in pulse widths since PMOS is more susceptible to NBTI; (2) NBTI together with process variation, induces more soft errors (similar to 19%) and thus needs to be considered, simultaneously, during circuit analysis. Experimental result shows that our SSER framework considering both process variation and aging is efficient (with multiple-order speedups) and achieves high accuracy (with <3% errors) when compared with Monte-Carlo SPICE simulation.
An incremental learning framework for estimating signal controllability in unit-level verification
(2007)
Wen, Charles H. -P.
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Wang, Li-C.
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Bhadra, Jayanta
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電信工程研究所
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Institute of Communications Engineering
Unit-level verification is a critical step to the success of full-chip functional verification for microprocessor designs. In the unit-level verification, a unit is first embedded in a complex software that emulates the behavior of surrounding units, and then a sequence of stimuli is applied to measure the functional coverage. In order to generate such a sequence, designers need to comprehend the relationship between boundaries at the unit under verification and at the inputs to the emulation software. However, figuring out this relationship can be very difficult. Therefore, this paper(1) proposes an incremental learning framework that incorporates an ordered-binary-decision-forest(OBDF) algorithm, to automate estimating the controllability of unit-level signals and to provide full-chip level information for designers to govern these signals. Mathematical analysis shows that the proposed OBDF algorithm has lower model complexity and lower error variance than the previous algorithms. Meanwhile, a commercial microprocessor core is also applied to demonstrate that controllability of input signals on the load/store unit in the microprocessor core can be estimated automatically and information about how to govern these signals can also be extracted successfully.
An Intelligent Analysis of Iddq Data for Chip Classification in Very Deep-Submicron (VDSM) CMOS Technology
(2012)
Chang, Chia-Ling (Lynn)
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Chang, Chia-Ching (Austin)
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Chan, Hui-Ling
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Wen, Charles H. -P.
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Bhadra, Jayanta
Iddq testing has been a critical integral component in test suites for screening unreliable devices. As the silicon technology keeps shrinking, Iddq values and their variation increase as well. Moreover, along with rapid design scaling, defect-induced leakage currents become less significant when compared to full-chip current and also make themselves less distinguishable. Traditional Iddq methods become less effective and cause more test escapes and yield loss. Therefore, in this paper, a new test method named sigma-Iddq testing is proposed and integrates (1) a variation-aware full-chip leakage estimator and (2) a clustering algorithm to classify chip without using threshold values. Experimental result shows that sigma-Iddq testing achieves a higher classification accuracy in a 45nm technology when compared to a single-threshold Iddq testing. As a result, both the process-variation and design-scaling impacts are successfully excluded and thus the defective chips can be identified intelligently.
An Online Thermal-Constrained Task Scheduler for 3D Multi-Core Processors
(2015)
Liao, Chien-Hui
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Wen, Charles H. -P.
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Chakrabarty, Krishnendu
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資訊工程學系
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電信工程研究所
Hotspots occur frequently in 3D multi-core processors (3D-MCPs) and they can adversely impact system reliability and lifetime. Moreover, frequent occurrences of hotspots lead to more dynamic voltage and frequency scaling (DVFS), resulting in degraded throughput. Therefore, a new thermal-constrained task scheduler based on thermal-pattern-aware voltage assignment (TPAVA) is proposed in this paper. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. Moreover, the proposed task scheduler integrates a vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs. Experimental results show that, compared with two previous methods, the proposed task scheduler can respectively lower hotspot occurrences by 47.13% and 53.91%, and improve throughput by 6.50% and 32.06%. As a result, TPAVA and VGVS are effectively for reducing occurrences of hotspots and optimizing throughput for 3D-MCPs under thermal constraints.
An Online Thermal-Pattern-Aware Task Scheduler in 3D Multi-Core Processors
(2017-12-01)
Liao, Chien-Hui
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Wen, Charles H. -P.
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電機工程學系
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電信工程研究所
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Department of Electrical and Computer Engineering
Hotspots occur frequently in 3D multi-core processors (3D-MCPs), and they may adversely impact both the reliability and lifetime of a system. We present a new thermally constrained task scheduler based on a thermal-pattern-aware voltage assignment (TPAVA) to reduce hotspots in and optimize the performance of 3D-MCPs. By analyzing temperature profiles of different voltage assignments, TPAVA pre-emptively assigns different initial operating-voltage levels to cores for reducing temperature increase in 3D-MCPs. The proposed task scheduler consists of an on-line allocation strategy and a new voltage-scaling strategy. In particular, the proposed on-line allocation strategy uses the temperature-variation rates of the cores and takes into two important thermal behaviors of 3D-MCPs that can effectively minimize occurrences of hotspots in both thermally homogeneous and heterogeneous 3D-MCPs. Furthermore, a new vertical-grouping voltage scaling (VGVS) strategy that considers thermal correlation in 3D-MCPs is used to handle thermal emergencies. Experimental results indicate that, when compared to a previous online thermally constrained task scheduler, the proposed task scheduler can reduce hotspot occurrences by approximately 66% (71%) and improve throughput by approximately 8% (2%) in thermally homogeneous (heterogeneous) 3D-MCPs. These results indicate that the proposed task scheduler is an effective technique for suppressing hotspot occurrences and optimizing throughput for 3D-MCPs subject to thermal constraints.
CASSER: A Closed-Form Analysis Framework for Statistical Soft Error Rate
(2013-10-01)
Chang, Austin C. -C.
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Huang, Ryan H. -M.
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Wen, Charles H. -P.
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
CMOS designs in the deep submicrometer era require statistical methods to accurately estimate the circuit soft error rate (SER). However, process variation increases the complexity of statistical characteristics related to transient faults, leading to considerable uncertainty in the behavior of soft errors. Regardless of the methods used, current statistical SER (SSER) frameworks invariably involve a tradeoff between accuracy and efficiency. This paper presents accurate cell models in first-order closed form to overcome this problem, thereby enabling the analysis of SSERs in a block-based fashion similar to statistical static timing analysis. These cell models are derived as a closed form in the proposed framework named CASSER, and remain precise under the assumption of a normal distribution for the process parameters. Experimental results demonstrate the efficiency (> 2-order times faster than the latest framework) and accuracy (< 3% error) of CASSER in estimating circuit SERs, when compared with the Monte Carlo SPICE simulation.
DAD-FF: Hardening Designs by Delay-Adjustable D-Flip-Flop for Soft-Error-Rate Reduction
(2020-04-01)
Lin, Dave Y. -W.
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Wen, Charles H. -P.
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電機工程學系
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Department of Electrical and Computer Engineering
For the safety-critical applications such as biomedical and automobile electronics, the system failure induced by soft errors becomes a major issue of reliability. However, most of the commercial cell libraries do not include radiation-hardened components to build a safety-critical design. Therefore, a delay-adjustable D-flip-flop (DAD-FF) is proposed together with a design flow to construct a radiation-hardened system by automation. To enable such radiation-hardened design into the current design flow, DAD-FF is characterized as a general cell and compiled as a patch in the NanGate FreePDK45 bulk 45-nm open cell library, as an example. The experimental results show that DAD-FF is capable of reducing $1.3\times 10<^>{10}\text{X}$ soft errors with respect to the standard flip-flop (STD-FF) and resisting over 99.999997% strikes of heavy ions. Meanwhile, four radiation-hardened benchmark circuits are synthesized with DAD-FF cell, and further used to prove the effectiveness against soft errors compared to a prior work, built-in soft-error resilience (BISER), with 18% area and 40% timing improvement. To sum up, DAD-FF is elaborated from the modeling at the device-level to the validation at the system-level and exhibits its strong robustness to soft errors.
Demystifying Iddq Data With Process Variation for Automatic Chip Classification
(2015-06-01)
Chang, Chia-Ling (Lynn)
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Wen, Charles H. -P.
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電機資訊學士班
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Undergraduate Honors Program of Electrical Engineering and Computer Science
Iddq testing is an integral component of test suites for the screening of unreliable devices. As the scale of silicon technology continues shrinking, Iddq values and associated fluctuations increase. In addition, increased design complexity makes defect-induced leakage currents difficult to differentiate from full-chip currents. Consequently, traditional Iddq methods result in more test escapes and yield loss. This brief proposes a new test method, called s-Iddq to provide the following: 1) Iddq analysis with process-parameter deduction and 2) the algorithm for automatic chip-classification called collective analysis without the need to manually determine threshold values. We randomly inserted a number of multiple defects into samples of ISCAS\' 89 and IWSL\'05 benchmark circuits. Experimental results demonstrate that the proposed s-Iddq method can achieve higher classification accuracy than single-threshold Iddq testing or sigma-Iddq in a 45-nm technology. The overall classification accuracy of the collective analysis achieve averaged 99.28% and 99.70% on s-Iddq data from process-parameter deductions with average-case search and multilevel search, respectively, demonstrating that the influence of process variation and design scaling can be significantly reduced to enable a better identification of defective chips.
(DENDIST)-E-2-FM: Flow Migration in Routing of OpenFlow-based Cloud Networks
(2013-01-01)
Lin, Wei-Chu
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Liu, Gen-Hen
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Kuo, Kuan-Tsen
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Wen, Charles H. -P.
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電機資訊學士班
A prior layer-2 routing algorithm-(DENDIST)-E-2 demonstrates advantages in throughput improvement, reroute period and failure recovery. Moreover, with the invention of software-defined networking (SDN), a revolutionary networking concept, dynamic routing protocols can embrace more flexible policy on per-flow basis. However, due to runtime complexity of dynamic routing, many issues on the practicality emerge and await to be resolved. Therefore, in this paper, we first apply (DENDIST)-E-2 to a SDN architecture and compare performances between dynamic-routing and flow-control mechanisms in a OpenFlow-based cloud network. Then, the flow-migration (FM) scheme, showing a better flow-control management, can be combined with (DENDIST)-E-2, and evolved into (DENDIST)-E-2-FM. At last, experimental results demonstrate that (DENDIST)-E-2-FM enables better feasibility in real-world applications, throughput improvement, sensitivity to reroute period and reduction in failure recovery time.
Deploying QoS-assured Service Function Chains with Stochastic Prediction Models on VNF Latency
(2017-01-01)
Lei, Tsung-Han
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Hsu, Yao-Tsung
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Wang, I-Chih
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Wen, Charles H. -P.
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電機工程學系
Current Network Function Virtualization (NFV) with Virtualized Network Functions (VNFs) running as virtual machines on commodity servers enables flexibility to Service Function Chaining (SFC). Specific applications may require Quality of Service (QoS) on end-to-end latency. However, the processing delay and the queuing delay of VNFs varies with virtual resource configurations (vCPU and vMemory), as well as physical usage (traffic amount, CPU utilization). Moreover, packet delays are randomly distributed, instead of a fixed value. To accurately model the latency distribution of one VNF, a prediction method using random-forest regression is proposed. Evaluation results show that our method can predict the latency distribution of the two sample VNFs with only 10% errors. On the basis of the model, a QoS-assured SFC deployment algorithm is also presented to guarantee end-to-end latency and bandwidth consumption of users. Experiments show that our algorithm enables high degree of scalability with polynomial runtime, and meanwhile maximizes user acceptance rates with 6% difference from the optimal solution from the mixed integer programming.
Diagnosing Multiple Byzantine Open-Segment Defects Using Integer Linear Programming
(2011-12-01)
Kao, Chen-Yuan
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Liao, Chien-Hui
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Wen, Charles H. -P.
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Faulty behaviors of open-segment defects are non-deterministic due to the Byzantine effect induced by the physical circuit layout. It is the test pattern and difficult for traditional ATPGs to manifest the corresponding faulty effect. Therefore, we propose a three-stage diagnosis approach for finding multiple open-segment defects. Stage one applies path tracing to help extract candidate fault sites from error outputs of failing patterns. An ILP solver in stage two effectively enumerates all fault combinations when considering fault candidates and simulation responses simultaneously. During stage three, fault simulation with support of physical information is responsible for identifying true open-segment defects by pruning false cases. Experimental results show good resolutions (only 1.7X and 1.5X total numbers of segments on average under 1,000 random and 5-detect patterns, respectively) for all ISCAS'85 circuits with 2-5 randomly-injected open-segment defects.
Dynamic Switch Migration in Distributed Software-Defined Networks to Achieve Controller Load Balance
(2019-03-01)
Xu, Yang
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Cello, Marco
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Wang, I-Chih
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Walid, Anwar
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Wilfong, Gordon
Multiple distributed controllers have been used in software-defined networks (SDNs) to improve scalability and reliability, where each controller manages one static partition of the network. In this paper, we show that dynamic mapping between switches and controllers can improve efficiency in managing traffic load variations. In particular, we propose balanced controller (BalCon) and BalConPlus, two SDN switch migration schemes to achieve load balance among SDN controllers with small migration cost. BalCon is suitable for the scenarios where the network does not require a serial processing of switch requests. For other scenarios, BalConPlus is more suitable, as it is immune to the switch migration blackout and does not cause any service disruption. Simulations demonstrate that BalCon and BalConPlus significantly reduce the load imbalance among SDN controllers by migrating only a small number of switches with low computation overhead. We also build a prototype testbed based on the open-source SDN framework RYU to verify the practicality and effectiveness of BalCon and BalConPlus. Experiment confirms the results of the simulations. It also shows that BalConPlus is immune to switch migration blackout, an adverse effect in the baseline BalCon.
Dynamic Voltage Assignment for Thermal-Constrained Task Scheduler on 3D Multi-Core Processors
(2015)
Liao, Chien-Hui
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Lin, Yu-Ze
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Wen, Charles H. -P.
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傳播研究所
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資訊工程學系
Thermal-constrained task scheduler for throughput optimization on 3D multi-core processors (3D-MCPs) has been studied extensively. Most task scheduler focused on thermal-aware task allocation to reduce hotspots, thereby maximizing throughput under thermal constraints. Rather than focusing on the thermal-aware task allocation as previous work does, this work targets on the voltage assignment. In this paper, dynamic voltage assignment is proposed to pre-emptively assign different voltage levels to cores frequently for reducing temperature increase in 3D-MCPs. Experimental results show that two previous task schedulers integrated with the proposed dynamic voltage assignment can lower hotspot occurrences by 62.31% and 59.09%, and improve throughput by 18.28% and 18.35%, respectively. As a result, task schedulers integrated with the proposed dynamic voltage assignment can be more effective to reduce occurrences of hotspots and optimize throughput for 3D-MCPs under thermal constraints.
EQVMP: Energy-efficient and QoS-aware Virtual Machine Placement for Software Defined Datacenter Networks
(2014-01-01)
Wang, Shao-Heng
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Huang, Patrick P. -W.
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Wen, Charles H. -P.
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Wang, Li-Chun
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資訊工程學系
To provide effective and reliable services, cloud datacenters need parallel computing and virtualization techniques. This work presents an improved virtual machine (VM) placement mechanism, called Energy efficiency and Quality of Service (QoS) aware VM Placement (EQVMP) to overcome the problem of unbalanced traffic load in switching on and off VMs for the purpose of energy saving. EQVMP combines three key techniques: (1) hop reduction, (2) energy saving and (3) load balancing. Hop reduction can regroup VMs to lower the traffic load among them. Energy saving techniques aim at choosing the appropriate servers. The proposed load balancing updates VM placement periodically. Our experimental results show that the proposed scheme can lower energy consumption and maintain QoS. We propose an evaluation score [1] to assess VM placement in terms of energy, delay and throughput. Comparing to other existing placement policies, our proposed mechanism can enhance system throughput by 25% and can have better evaluation score.
ERIC: Economical & Reconfigurable HybrId-band Control for Software-Defined Datacenter Network
(2016)
Suo, Cheng
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Tsai, I-Chen
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Wen, Charles H. -P.
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電機學院
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College of Electrical and Computer Engineering
Datacenter networks (particularly, in clouds) nowadays support varieties of services from customers, and a novel paradigm, Software Defined Networking (SDN), is proposed to offer flexible application-aware management of these networks. However, as networks keep scaling up, many difficulties arise. Unlike prior studies on the data plane in SDN, this paper investigates the increasing complexity from deploying the control plane and proposes a novel economical and reconfigurable hybrid-band control mechanism (named ERIC) for large-scale SDN networks. Comparing to the state-of-the-art control mechanism (out-of band), ERIC is much simpler and provides more reliability. Moreover, the number of switches used in the ERIC control plane is only 25% of that in the out-of-band control plane with 9%, throughput differences. As a result, ERIC is proven suitable for datacenters due to low cost and high flexibility and can be applied to large-scale network deployments.