Browsing by Author "Wen, K. A."

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A flexible mixed-signal/RF CMOS technology for implantable electronics applications
(2010-04-01)
Hsieh, C. Y.
;
Chen, C. S.
;
Tsou, W. A.
;
Yeh, Y. T.
;
Wen, K. A.
A novel post-CMOS fabrication process has been developed to transform a 0.18 mu m 1P6M mixed-signal/RF CMOS (complementary metal oxide semiconductor)-integrated circuit chips fabricated on an 8 inch SOI (silicon-on-insulator) wafer into flexible devices sandwiched between biocompatible material (10 mu m parylene-C on both sides in this case) and enables future implementation of implantable and fully integrated electronic devices. The functionality of the flexible integrated circuits is demonstrated by a low phase noise RF CMOS VCO (voltage-controlled oscillator) circuit in a ring oscillator configuration that operates at a few hundred MHz to GHz. We report here the associated post-processing technology to make these flexible IC chips and the characterization of both MOS transistors and the demonstration circuit on the flexible IC chip under bending stresses.
A flexible mixed-signal/RF CMOS technology for implantable electronics applications
(2010-04-01)
Hsieh, C. Y.
;
Chen, C. S.
;
Tsou, W. A.
;
Yeh, Y. T.
;
Wen, K. A.
A novel post-CMOS fabrication process has been developed to transform a 0.18 mu m 1P6M mixed-signal/RF CMOS (complementary metal oxide semiconductor)-integrated circuit chips fabricated on an 8 inch SOI (silicon-on-insulator) wafer into flexible devices sandwiched between biocompatible material (10 mu m parylene-C on both sides in this case) and enables future implementation of implantable and fully integrated electronic devices. The functionality of the flexible integrated circuits is demonstrated by a low phase noise RF CMOS VCO (voltage-controlled oscillator) circuit in a ring oscillator configuration that operates at a few hundred MHz to GHz. We report here the associated post-processing technology to make these flexible IC chips and the characterization of both MOS transistors and the demonstration circuit on the flexible IC chip under bending stresses.
CMOS 0.18 mu m Standard Process Capacitive MEMS High-Q Oscillator with Ultra Low-Power TIA Readout System
(2014)
Kuo, F. Y.
;
Chang, C. F.
;
Wen, K. A.
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents the first monolithic ultra-low power MEMS oscillator that can be manufactured in the ASIC compatible standard CMOS process and monolithically integrated with TIA circuitry. It is designed for high Q value and moderate motional impedance under strict design constraints of the standard fabrication process. A high gain ultra-low power sustaining TIA amplifier circuit is compactly integrated with the resonator structure on a single die for low-power 32 kHz clock generation. The proposed 1.69 mu W MEMS oscillator can be embedded in common SoC applications monolithically to provide clock sources.
Standard 0.18um 1P6M CMOS IC foundry flow for accelerometer, analog readout circuit and wafer level capping package integration
(2011)
Huang, C. J.
;
Chen, C. S.
;
Wen, K. A.
;
Cheng, Y. T.
;
Chen, J. Y.
The first standard CMOS IC foundry flow is presented for the monolithic integration of MEMS sensor, analog readout circuit and wafer level capping on standard 0.18um 1P6M technology. The sensor and circuit parts are fabricated at first on the same 8 '' substrate using a standard 0.18um 1P6M CMOS process. The sensor part is then micromachined and released by a foundry-based post-CMOS DRIE process followed by wafer level capping. The test vehicle for the proposed integration flow contains a single-axial accelerometer, analog readout circuit with input common-mode feedback and QFN64 package. The measurement results show that the whole system can have 206mV/g of sensitivity and output noise is less than 250 mu g/root Hz. The proposed methodology has led a promising way for integrating MEMS, IC and package in a conventional IC foundry manufacturing flow.
Temperature-dependent yield effects on composite beams used in CMOS MEMS
(2013-03-01)
Kuo, F. Y.
;
Chang, C. S.
;
Liu, Y. S.
;
Wen, K. A.
;
Fan, L. S.
This paper presents an experimentally verified analytical model of temperature-dependent yield effects on the curvatures of composite beam structures used in complementary metal-oxide semiconductor microelectromechanical systems (CMOS MEMS). The temperature-dependent effects on composite beam curvatures of a thermal process can be predicted by extracting key parameters from the measured curvatures of a limited number of CMOS MEMS composite-layer combinations. The effects due to thermal history in MEMS packaging, which change the characteristics of beam curvatures due to material yield, are further analyzed. The models are verified with measured results from beam structures fabricated by an application-specific integrated circuit-compatible 0.18 mu m 1P6M CMOS MEMS process using a white light interferometer. These models can be applied in electronic design automation tools to provide good prediction of temperature-dependent properties related to CMOS MEMS beam curvature, such as sensing capacitance, for monolithic sensor system on chip design.