Browsing by Author "Wen, Ting-Ting"

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Comparison of Electrical Characteristics of N-type Silicon Junctionless Transistors with and without Film Profile Engineering by TCAD Simulation
(2015)
Tsai, Jung-Ruey
;
Lin, Horng-Chih
;
Chang, Hsiu-Fu
;
Shie, Bo-Shiuan
;
Wen, Ting-Ting
Field-effect transistors (FETs) with junctionless (JL) channels have recently attracted much attention for various applications, such as metal-oxide semiconductor thin-film transistors (TFTs) [1], memory devices [2] and Si nanowire TFTs [3, 4]. The Si junctionless (JL) transistors employing high dopant concentration (>= 10(19) cm(-3)) in the source, drain, and nano-scaled channel have been demonstrated to provide excellent electrical characteristics. More recently, film profile engineering (FPE) concept for fabricating downscaled ZnO and IGZO TFTs [5, 6] have been proposed to obtain high-on/off current ratio and great subthreshold swing. Nevertheless, it emphasizes a significant issue of source/drain (S/D) series resistance on the downscaled device performance that needs to be further verified. In this work, electrical performance of downscaled N-type Si JL TFTs with FPE channel and conventional ones will be compared with each other by Sentaurus technology computer aided design (TCAD) simulation [7].
Effect of dose loss of phosphorus on capacitance-voltage characteristics of n-type poly-Si junctionless thin-film transistors
(2017-01-01)
Tsai, Jung-Ruey
;
Wen, Ting-Ting
;
Lin, Horng-Chih
;
交大名義發表
;
電子工程學系及電子研究所
This study examines the effects of the dose loss of phosphorus on the capacitance-voltage characteristics of an n-type polycrystalline silicon junctionless (JL) transistor using experimental, analytical and simulated analyses. It clearly demonstrates that the gate voltage increases as the doping concentration in the channel of the JL transistor decreases, maintaining constant capacitance because the depletion region is easily formed at the surface of the channel with a low doping concentration. The critical gate voltage (V-GC) is defined as the applied gate voltage that induces the gate capacitance at the kink of the C-V curve. The simulated results clearly suggest that the critical gate voltage increases linearly with the percentage of dose loss of phosphorus.
ENGINEERED THRESHOLD VOLTAGE IN ALGAN/GAN HEMTS FOR NORMALLY-OFF OPERATION
(2015)
Tsai, Jung-Ruey
;
Chang, Yi-Sheng
;
Wei, Kuo-Shu
;
Wen, Ting-Ting
;
奈米中心
This work proposed the normally-off gate-recessed AlGaN/GaN high electron mobility transistors (HEMTs) with more suitable threshold voltages by adjusting the Al mole fraction in the various AlGaN layer thickness under the gate region. It is found that the slope of threshold voltage versus Al mole fraction curves is decreased with decreasing the thickness of AlGaN layer due to the decrease of piezoelectric effect on 2DEG concentration.
Reliability Analysis of Amorphous Silicon Thin-Film Transistors during Accelerated ESD Stress
(2015)
Tsai, Jung-Ruey
;
Wen, Ting-Ting
;
Yang, Shao-Ming
;
Sheu, Gene
;
Chang, Ruey-Dar
This work investigates the degradation of electrical characteristics of amorphous silicon thin-film transistors during the accelerated ESD stress with a 40V high voltage and a high/low current of 2 mA/0.1 mu A conditions. Both the leakage current and the threshold voltage shift are severe as the accelerated ESD stress applied at the gate region. The 40V accelerated ESD stress with a high current has more severe impact on the electrical performance of device than that with a low current.