Browsing by Author "Weng, Wu-Te"

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A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO(2)/poly-gate complementary metal oxide semiconductor technology
(2010-04-01)
Weng, Wu-Te
;
Lee, Yao-Jen
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
This study examines the effects of plasma-induced damage (PID) both on advanced SiO(2)/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO(2)/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. (C) 2010 Elsevier Ltd. All rights reserved.
A comparison of plasma-induced damage on the reliability between high-k/metal-gate and SiO2/poly-gate complementary metal oxide semiconductor technology
(2010-04-01)
Weng, Wu-Te
;
Lee, Yao-Jen
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
This study examines the effects of plasma-induced damage (PID) both on advanced SiO2/poly-gate and Hf-based high-k/dual metal-gates transistors processed with advanced complementary metal-oxide-semiconductor (CMOS) technology. In addition to the gate dielectric degradations, this study demonstrates the PID impacts on transistor reliability including the positive bias temperature instability (PBTI) of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and the negative bias temperature instability (NBTI) of p-channel MOSFETs with gate dielectric thickness scaling. This study shows that high-k/metal-gate transistors are more robust against PID than conventional SiO2/poly-gate transistors with similar physical thickness. Finally this study proposes a model that successfully explains the observed experimental trends in the presence of PID for advanced high-k/metal-gate CMOS technology. (C) 2010 Elsevier Ltd. All rights reserved.
Effects of Plasma Damage on Metal-insulator-Metal Capacitors and Transistors for Advanced Mixed-Signal/Radio-Frequency Metal-Oxide-Semiconductor Field-Effect Transistor Technology
(2009-08-01)
Weng, Wu-Te
;
Lee, Yao-Jen
;
Lin, Hong-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
The effects of damage on mixed-signal (MS)/radio-frequency (RF) circuits integrated with metal-insulator-metal (MIM) capacitors and advanced metal-oxide-semiconductor field-effect transistors (MOSFETs) are studied in this work. The impact of damage on an MIM oxide is evaluated by connecting its capacitor top metal (CTM) to an upper-level metal with a large antenna ratio (AR(CTM)) used in an actual CTM circuit connected to an interconnect. In addition to the dielectric degradation of a transistor, we also investigate the damage-enhanced negative bias temperature instability (NBTI) degradation of a transistor with its gate electrode connected to an MIM capacitor with a large ARCTM for various gate oxide thicknesses. A model is proposed to explain the experimentally observed dependence of NBTI degradation on AR(CTM) and accurately simulate failure distributions in the presence of plasma damage. (C) 2009 The Japan Society of Applied Physics