Browsing by Author "Wey, WS"

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A CMOS delta-sigma true RMS converter
(2000-02-01)
Wey, WS
;
Huang, YC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Conventionally, monolithic electronics true rms converters are constructed by bipolar circuitry, This paper describes a new architecture based on delta-sigma (Delta Sigma) modulation to realize a low-cost rms converter in CMOS technologies, especially intended for handheld digital multimeters. The signal-to-quantization noise ratio as well as transfer characteristics of this architecture have been deduced to obtain initial design parameters. The use of an indirect charge transfer technique makes the converter gain depend only on an on-chip capacitor ratio, reducing gain drift and offering good gain accuracy, Measured results show that this converter achieves a signal-to-noise ratio of 88 dB and a relative error of +/-0.2% for arbitrary inputs with a signal crest factor up to three. The signal bandwidth exceeds 50 kHz, and the full-scale input range is greater than 0.4 V-rms. Without trimming and calibration, this converter has an absolute gain error less than +/-0.4%. This chip is fabricated in a 0.8-mu m double-poly; double-metal CMOS process and occupies active area of 1 mm(2).
A CMOS rms-to-dc converter using Delta Sigma multiplier-divider
(1999)
Wey, WS
;
Huang, YC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel topology for CMOS Delta Sigma rms-to-dc converters is described. Analysis shows that the proposed topology is insensitive to most circuit imperfections except offset voltages. A test circuit of a 1st-order single-ended rms-to-dc converter is realized in a 0.8 mu m double-poly CMOS process. Experimental results demonstrate that input waveforms with crest factors as high as 3 can be measured at the 800mV full-scale input level. It provides a maximum relative error of +/-1% of reading.
Second-order delta-sigma modulation with interfered reference
(2001-02-01)
Huang, YC
;
Wey, WS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A delta-sigma (Delta Sigma) modulator has been traditionally analyzed by assuming its reference to be constant, but practically the reference may be interfered and thus vary with time. For an interfered reference modulator, the performance of quantization noise is degraded by quantization noise leakage due to interfered feedback. In this paper, a systematic study for observing the behavior of a second-order modulator with an interfered references is presented, based on a linear modeling, spectral analysis, and beharioral simulations. An analytical form of the output of a a Delta Sigma modulator with an interfered feedback is obtained and compared with behavioral simulation. Due to the agreement between the theoretical calculation and the behavioral simulation results, it is concluded that the quantization noise leakage should be considered for describing the behavior of the Delta Sigma modulators more precisely.