Browsing by Author "Whang, SJ"

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Effect of surface NH3 anneal on the physical and electrical properties of HfO2 films on Ge substrate
(2004-05-10)
Wu, N
;
Zhang, QC
;
Zhu, CX
;
Yeo, CC
;
Whang, SJ
Metal-oxide-semiconductor capacitors were fabricated on germanium substrates by using metalorganic-chemical-vapor-deposited HfO2 as the dielectric and TaN as the metal gate electrode. It is demonstrated that a surface annealing step in NH3 ambient before the HfO2 deposition could result in significant improvement in both gate leakage current and the equivalent oxide thickness (EOT). It was possible to achieve a capacitor with an EOT of 10.5 Angstrom and a leakage current of 5.02x10(-5) A/cm(2) at 1 V gate bias. X-ray photoelectron spectroscopy analysis indicates the formation of GeON during surface NH3 anneal. The presence of Ge was also detected within the HfO2 films. This may be due to Ge diffusion at the high temperature (similar to400 degreesC) used in the chemical-vapor deposition process. (C) 2004 American Institute of Physics.
Low temperature MOSFET technology with Schottky barrier source/drain, high-K gate dielectric and metal gate electrode
(2004-10-01)
Zhu, SY
;
Yu, HY
;
Chen, JD
;
Whang, SJ
;
Chen, JH
Both P- and N-channel MOSFET's with Schottky barrier silicide source/drain (S/D), high-K gate dielectric and metal gate were successfully fabricated using a simplified low temperature process. The highest temperature after the high-K dielectric formation is 420degreesC. PMOSFETs with PtSi S/D show excellent electrical performance of an I-on/I-off similar to 10(7)-10(8) and a subthreshold slope of 66 mV/dec, similar to those formed by a normal process with an optimized sidewall spacer. NMOSFETs with DySi2-x S/D have similar to3 orders of magnitude larger I-off than that of PMOSFETs and show two slopes in the subthreshold region, resulting in the I-on/I-off similar to 10(5) at low drain voltage. It can be attributed to the relatively higher barrier height (Phi(n)) of DySi2-x/n-Si than that of PtSi/p-Si (Phi(p)) and the rougher DySi2-x film. Adding a thin intermediate Ge layer (similar to1nm) between Dy and Si can improve the film morphology significantly. As a result, the improved performance of N-MOSFET is observed. (C) 2004 Published by Elsevier Ltd.
Schottky-barrier S/D MOSFETs with high-K gate dielectrics and metal-gate electrode
(2004-05-01)
Zhu, SY
;
Yu, HY
;
Whang, SJ
;
Chen, JH
;
Shen, C
This letter presents a low-temperature process to fabricate Schottky-barrier silicide source/drain transistors (SSDTs) with high-kappa gate dielectric and metal gate. For p-channel SSDTs (P-SSDT) using PtSi source/drain (S/D), excellent electrical performance of I-on/I-off similar to 10(7) - 10(8) and subthreshold slope of 66 mV/dec have been achieved. For n-channel SSDTs (N-SSDTs) using DySi2-x S/D, I-on/I-off can reach similar to 10(5) at V-ds of 0.2 V with two subthreshold slopes of 80 and 340 mV/dec. The low-temperature process relaxes the thermal budget of high-kappa dielectric and metal-gate materials to be used in the future generation CMOS technology.