Browsing by Author "Wong, Cheng-Chi"

Now showing 1 - 11 of 11

A 0.22nJ/b/iter 0.13 mu m turbo decoder chip using inter-block permutation interleaver
(2007)
Wong, Cheng-Chi
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Tang, Cheng-Hao
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Lai, Ming-Wei
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Zheng, Yan-Xiu
;
Lin, Chien-Ching
This paper presents a high speed turbo decoder containing 32 MAP decoders with a inter-block permutation interleaver. The proposed butterfly network guarantees contention-free property and promises parallel processing of turbo decoder without performance degradation. In addition, our approach also features a relocated radix-2 x 2 ACS structure to reduce the critical path delay. After manufacturing by 0.13 mu m CMOS process, the test results show the energy efficiency is 0.22nJ/b/iter in the 160Mb/s data rate.
A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System
(2009)
Wong, Cheng-Chi
;
Lee, Yung-Yu
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Chang, Hsie-Chia
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a three-stage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm(2) chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.
A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System
(2009)
Wong, Cheng-Chi
;
Lee, Yung-Yu
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a three-stage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm(2) chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.
A 188-size 2.1mm(2) Reconfigurable Turbo Decoder Chip with Parallel Architecture for 3GPP LTE System
(2009-01-01)
Wong, Cheng-Chi
;
Lee, Yung-Yu
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a turbo decoder chip supporting all 188 block sizes in 3GPP LTE standard. The design allows 1, 2, 4, or 8 SISO decoders to concurrently process each block size, and the number of iteration can be adjusted. Moreover, a three-stage network is utilized to connect multiple memory modules and multiple SISO decoders. After fabricated in 90nm process, the 2.1mm(2) chip can achieve 129Mb/s with 219mW for the 6144-bit block after 8 iterations.
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis
(2013-11-01)
Lin, Chen-Yang
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Wong, Cheng-Chi
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Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a multiple code-rate turbo decoder using the reciprocal dual trellis to improve the hardware efficiency. For a convolutional code with code rate k/(k + 1), its corresponding reciprocal dual code with rate 1/(k + 1) has smaller codeword space than the original code while k > 1, leading to a simplified trellis of the high code-rate code. The proposed decoder architecture can decode code rate k/(k + 1) constituent convolutional codes for k = 1, 2, 4, 8, and 16. Moreover, two parallel soft-in/soft-out (SISO) decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm(2) core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.
A 40 nm 535 Mbps Multiple Code-Rate Turbo Decoder Chip Using Reciprocal Dual Trellis
(2012)
Lin, Chen-Yang
;
Wong, Cheng-Chi
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a turbo decoder chip which can decode code rate k/(k + 1) constituent convolutional codes for k = 1, 2, 4, 8, and 16. After replacing the constituent code by its code rate 1/(k + 1) reciprocal dual code, we can derive a smaller codeword space and design a simpler decoding trellis structure for high code-rate SISO decoder. In addition, two parallel SISO decoders are exploited in our turbo decoder by using the quadratic permutation polynomial (QPP) interleaver to improve the decoding speed. After fabricated in 1P9M CMOS 40 nm process, the proposed decoder with 1.27 mm(2) core area can achieve 535 Mbps throughput at 8/9 code rate, and the energy efficiency is 0.068 nJ/bit/iteration at 0.9 V.
A Multiple Code-Rate Turbo Decoder Based on Reciprocal Dual Trellis Architecture
(2010)
Lin, Chen-Yang
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Wong, Cheng-Chi
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To increase channel efficiency for high throughput systems, the high code-rate schemes are usually required. However, conventional turbo decoders in high code-rate usually apply high radix trellis structure, and the complexity of the trellis increases exponentially according to the code-rate. In this paper, the reciprocal dual trellis is applied to reduce the trellis complexity and a multiple code-rate turbo decoder is proposed. A sign magnitude representation is also introduced to lower the hardware complexity. The puncturing methodology is applied to WCDMA system as a case study of high code-rate turbo codes, and the investigated code-rates are 1/3, 1/2, 2/3, and 4/5. The simulation results are also shown in this paper. Fabricated with CMOS 90nm process, the proposed decoder containing 370K logic gates and 58kb storage units can achieve 101Mb/s with 80mW at code-rate 4/5.
An Area Efficient Radix-4 Reciprocal Dual Trellis Architecture for a High-Code-Rate Turbo Decoder
(2015-01-01)
Lin, Chen-Yang
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Wong, Cheng-Chi
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Chang, Hsie-Chia
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This brief presents an area-efficient turbo decoder based on the reciprocal dual trellis. In this brief, the radix-4 structure is introduced into the reciprocal dual trellis for throughput enhancement, and a sign-arrangement technique is developed to simplify the hardware and reduce the critical path of the recursion metric unit. To further reduce the hardware complexity, a time-multiplexing method with no degradation of throughput is also presented to save half of the extrinsic units, leading to a 15% hardware reduction of the soft-in/soft-out decoder. After implementation by CMOS 90-nm process, the proposed turbo decoder containing 600 k-gates and 152-kb SRAM can achieve 425 Mb/s with 310-mW power consumption at 8/9 code rate. The post-simulation results show that the proposed methods provide a hardware-efficient solution for turbo decoders exploiting high-code-rate operations.
High-Efficiency Processing Schedule for Parallel Turbo Decoders Using QPP Interleaver
(2011-06-01)
Wong, Cheng-Chi
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Chang, Hsie-Chia
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a high-efficiency parallel architecture for a turbo decoder using a quadratic permutation polynomial (QPP) interleaver. Conventionally, two half-iterations for different component codewords alternate during the decoding flow. Due to the initialization calculation and pipeline delays in every half-iteration, the functional units in turbo decoders will be idle for several cycles. This inactive period will degrade throughput, especially for small blocks or high parallelism. To resolve this issue, we impose several constraints on the QPP interleaver and rearrange the processing schedule; then the following half-iteration can be executed before the completion of the current half-iteration. Thus, it can eliminate the idle cycles and increase the efficiency of functional units. Based on this modified schedule with 100% efficiency, a parallel turbo decoder which contains 32 radix-2(4) SISO decoders is implemented with 90 nm technology to achieve 1.4 Gb/s while decoding size-4096 blocks for 8 iterations.
Reconfigurable Turbo Decoder With Parallel Architecture for 3GPP LTE System
(2010-07-01)
Wong, Cheng-Chi
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This brief presents a parallel architecture for the turbo decoder using the quadratic permutation polynomial inter-leaver. The supported block size ranges from 40 to 6144 with an increment of 8, and thus, it includes 188 sizes in the 3rd Generation Partnership Project Long Term Evolution standard. The proposed design can allow one, two, four, or eight soft-in/soft-out decoders to process each block with configurable iterations. To support all data transmissions in the parallel design, a multistage network with low complexity is also utilized. Moreover, a robust path metric initialization is given to improve the performance loss in small blocks and high parallelism. After fabrication in the 90-nm process, the 2.1-mm(2) chip can achieve 130 Mb/s with 219 mW for the size-6144 block and eight iterations.
Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture
(2010-02-01)
Wong, Cheng-Chi
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Lai, Ming-Wei
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Lin, Chien-Ching
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Chang, Hsie-Chia
;
Lee, Chen-Yi
This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.