Browsing by Author "Wong, H. -S. Philip"

Now showing 1 - 9 of 9

AC stress and electronic effects on SET switching of HfO2 RRAM
(2017-08-28)
Liu, Jen-Chieh
;
Magyari-Kope, Blanka
;
Qin, Shengjun
;
Zheng, Xin
;
Wong, H. -S. Philip
An AC stress test was performed to investigate the accompanying electronic effects in a HfO2 resistive random access memory during the SET transition, which featured a sudden decrease in resistance. Comparing the DC and AC measurement results indicated the pronounced influence of interrupted stress on both the mean values and variations of time to SET. First-principles calculations suggested that the charge states (+2, +1, or neutral) of oxygen vacancies affect the migration barrier for forming oxygen vacancy clusters. Therefore, a charge-state-dependent SET model is proposed to include the additional electronic effects induced by the dynamics of electron trapping and detrapping in oxygen vacancies during AC stress. A trimodal Weibull fitting based on the proposed model reproduced the experimental time to SET distributions obtained in a wide range of AC stress conditions. Published by AIP Publishing.
Design and Optimization Methodology for 3D RRAM Arrays
(2013)
Deng, Yexin
;
Chen, Hong-Yu
;
Gao, Bin
;
Yu, Shimeng
;
Wu, Shih-Chieh
3D RRAM arrays are studied at the device-and architecture-levels. The memory cell performance for a horizontal cross-point is shown experimentally to be essentially comparable to vertical pillar-around geometry. Array performances (read/write, energy, and speed) of different 3D architectures are investigated by SPICE simulation, showing horizontal stacked RRAM is superior but suffers from higher bit cost. Adopting a bi-layer pillar electrode structure is demonstrated to enlarge the array size in 3D vertical RRAM. Design guidelines are proposed for the 3D VRRAM: it shows that increasing the number of stacks of VRRAM while keeping the total bits the same, as well as scaling of feature size (F), are critical for reducing RC delay and energy consumption.
Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector-MTJ Cooptimization
(2020-08-01)
Chiang, Hung-Li
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Chen, Tzu-Chiang
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Song, Ming-Yuan
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Chen, Yu-Sheng
;
Chiu, Jung-Piao
To increase the density of magnetoresistive random accessmemory (MRAM) beyond the 1T1MTJMRAM cell in use today, the design space for 1S1MTJ MRAM array is analyzed by cooptimizing both selectors and MTJs. Current low-resistance MTJs for 1T1MTJ MRAM are not suitable for 1S1MTJ MRAM. Threshold-type selectors would induce a strong read disturb on the MTJ due to the snapback voltage (V-TH-V-HOLD) when the selector is turned on. Also, exponential-type selectorswould degrade the read margin (RM) due to its large ON-state resistance. When using existing selectors to achieve a 1-M-bit 1S1MTJ array, it is necessary to adjust the product of resistance and area (RA) and the diameter of the MTJ. An MTJ with the RA = 15 Omega . mu m(2) and the diameter = 50 nm can meet the criterion of RM > 10% for both exponential-type selectors (exponential slope = 300-500 mV/decade with the current density similar to 1 MA/cm(2)) and threshold-type selectors (V-TH-V-HOLD similar to 250 mV). A design space accommodating a selector variation of around 1% can be found for MTJs with tunnel magnetoresistance ratio (TMR) < 250%. With an increased TMR of 250%-350% of the MTJ, the tolerance of variations for exponential-type selectors and threshold-type selectors can be improved to 2% and 4%, respectively. This provides a chance for the 1S1MTJ MRAM with existing selectors.
Multi-level control of conductive nano-filament evolution in HfO2 ReRAM by pulse-train operations
(2014-06-07)
Zhao, L.
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Chen, H. -Y.
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Wu, S. -C.
;
Jiang, Z.
;
Yu, S.
Precise electrical manipulation of nanoscale defects such as vacancy nano-filaments is highly desired for the multi-level control of ReRAM. In this paper we present a systematic investigation on the pulse-train operation scheme for reliable multi-level control of conductive filament evolution. By applying the pulse-train scheme to a 3 bit per cell HfO2 ReRAM, the relative standard deviations of resistance levels are improved up to 80% compared to the single-pulse scheme. The observed exponential relationship between the saturated resistance and the pulse amplitude provides evidence for the gap-formation model of the filament-rupture process.
Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication
(2017-12-01)
Chen, Hong-Yu
;
Brivio, Stefano
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Chang, Che-Chia
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Frascaroli, Jacopo
;
Hou, Tuo-Hung
Emerging non-volatile memory technologies are promising due to their anticipated capacity benefits, non-volatility, and zero idle energy. One of the most promising candidates is resistive random access memory (RRAM) based on resistive switching (RS). This paper reviews the development of RS device technology including the fundamental physics, material engineering, three-dimension (3D) integration, and bottom-up fabrication. The device operation, physical mechanisms for resistive switching, reliability metrics, and memory cell selector candidates are summarized from the recent advancement in both industry and academia. Options for 3D memory array architectures are presented for the mass storage application. Finally, the potential application of bottom-up fabrication approaches for effective manufacturing is introduced.
Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap
(2009-02-01)
Wei, Lan
;
Deng, Jie
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Chang, Li-Wen
;
Kim, Keunwoo
;
Chuang, Ching-Te
We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-kappa/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.
Statistical Study of RRAM MLC SET Variability Induced by Filament Morphology
(2017-01-01)
Hsu, Chung-Wei
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Zheng, Xin
;
Wu, Yi
;
Hou, Tuo-Hung
;
Wong, H. -S. Philip
This paper establishes the correlation between RRAM multilevel-cell (MLC) stochastic SET variability and random telegraph noise (RTN). We show that a smaller diameter (d(D)) of locally connecting/rupturing conductive filament (CF) and larger distance of gap (d(G)) between CF and electrode demonstrate both steeper Weibull slope beta with a relaxed SET-disturb margin by 0.4 V and 36x improvement in RTN robustness. This is achieved by lower current compliances (I-COMP) of 100 mu A and larger RESET stopping voltage (V-RESET) of -4.5 V for smaller dD and larger dG with leaving less residual oxygen vacancies (V-o(+2)) in the gap region. Results from the Kinetic Monte Carlo (KMC) modeling also support these findings.
Wafer-scale single-crystal hexagonal boron nitride monolayers on Cu (111)
(2020-03-01)
Chen, Tse-An
;
Chuu, Chih-Piao
;
Tseng, Chien-Chih
;
Wen, Chao-Kai
;
Wong, H. -S. Philip
Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore's law of the number of transistors in an integrated circuit(1). One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering(2,3). Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces(4) or bulk copper foils(5). However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films(6,7). Growing single-crystal hBN on such high-symmetry surface planes as Cu (111)(5,8) is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics.
Wafer-scale single-crystal hexagonal boron nitride monolayers on Cu (111)
(1970-01-01)
Chen, Tse-An
;
Chuu, Chih-Piao
;
Tseng, Chien-Chih
;
Wen, Chao-Kai
;
Wong, H. -S. Philip
The epitaxial growth of single-crystal hexagonal boron nitride monolayers on a copper (111) thin film across a sapphire wafer suggests a route to the broad adoption of two-dimensional layered semiconductor materials in industry. Ultrathin two-dimensional (2D) semiconducting layered materials offer great potential for extending Moore's law of the number of transistors in an integrated circuit(1). One key challenge with 2D semiconductors is to avoid the formation of charge scattering and trap sites from adjacent dielectrics. An insulating van der Waals layer of hexagonal boron nitride (hBN) provides an excellent interface dielectric, efficiently reducing charge scattering(2,3). Recent studies have shown the growth of single-crystal hBN films on molten gold surfaces(4) or bulk copper foils(5). However, the use of molten gold is not favoured by industry, owing to its high cost, cross-contamination and potential issues of process control and scalability. Copper foils might be suitable for roll-to-roll processes, but are unlikely to be compatible with advanced microelectronic fabrication on wafers. Thus, a reliable way of growing single-crystal hBN films directly on wafers would contribute to the broad adoption of 2D layered materials in industry. Previous attempts to grow hBN monolayers on Cu (111) metals have failed to achieve mono-orientation, resulting in unwanted grain boundaries when the layers merge into films(6,7). Growing single-crystal hBN on such high-symmetry surface planes as Cu (111)(5,8) is widely believed to be impossible, even in theory. Nonetheless, here we report the successful epitaxial growth of single-crystal hBN monolayers on a Cu (111) thin film across a two-inch c-plane sapphire wafer. This surprising result is corroborated by our first-principles calculations, suggesting that the epitaxial growth is enhanced by lateral docking of hBN to Cu (111) steps, ensuring the mono-orientation of hBN monolayers. The obtained single-crystal hBN, incorporated as an interface layer between molybdenum disulfide and hafnium dioxide in a bottom-gate configuration, enhanced the electrical performance of transistors. This reliable approach to producing wafer-scale single-crystal hBN paves the way to future 2D electronics.