Browsing by Author "Wong, SC"

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A CMOS mismatch model and scaling effects
(1997-06-01)
Wong, SC
;
Pan, KH
;
Ma, DJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model, Mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches, SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations, In addition, a root n-law model is developed for modeling gate-finger dependence of mismatch.
A CMOS mismatch model and scaling effects
(1997-06-01)
Wong, SC
;
Pan, KH
;
Ma, DJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, a novel single-pair mismatch model for short-channel MOS devices is developed, and scaling effects of mismatch distributions are investigated based on the model, Mismatch effect is modeled with threshold voltage, current factor, source resistance, and body factor mismatches, SPICE mismatch simulation is defined with mismatch parameters extracted from the model for accurate offset estimation in circuit simulation. Scaling effects with device size are investigated based on statistical mismatch data, and the results indicate that CMOS mismatch is induced by both local edge roughness and global variations, In addition, a root n-law model is developed for modeling gate-finger dependence of mismatch.
A study of tilt angle effect on Halo PMOS performance
(1998-09-01)
Su, JG
;
Wong, SC
;
Huang, CT
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The Halo structure is usually adopted in deep submicrometer MOS devices for punchthrough prevention. The tilt angle of the Halo implant determines the dopant distribution which induces anti-punchthrough operation. In this paper, we investigate the impact of the tilt angle on the Halo PMOS device performance via two-dimensional (2D) simulations. We find that the ratio of on-current to off-current is constant for all tilt angles of Halo implant, implying an equivalent DC performance for all tilt angles. The equivalence can be traced back to a self compensation between the body factor and source resistance. The result :implies that a low tilt angle should be adopted for Halo devices, for it gives a small threshold voltage and thus a high noise margin. The methodology used in analyzing body factor and source resistance can also be applied to analyze other devices. (C) 1998 Elsevier Science Ltd. All rights reserved.
An accurate RF CMOS gate resistance model compatible with HSPICE
(2004)
Lin, HW
;
Chung, SS
;
Wong, SC
;
Huang, GW
;
電子工程學系及電子研究所
Two important models, which are crucial to the RF CMOS, are the gate resistance and substrate resistance. Both are closely related to the development of accurate device and/or circuit models, such as noise. From the experimental observations, we found that the gate resistance depends largely on the bias and temperature. It will greatly impact the device performance at high frequency. For the first time, a simple and analytical physical-based gate resistance model is developed in this paper and has been implemented in Spice. The gate resistance is modeled by a parallel interconnection of the intrinsic gate resistance and a resistance coupled from the channel. The Spice simulation result of this model is more accurate than that of using a constant R-g model. A constant Rg model will overestimate the value of Y-11. While, in contrast, the proposed nonlinear gate resistance model with both bias and frequency dependent feature can achieve very good accuracy.
An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits
(2000-05-01)
Wong, SC
;
Lee, TGY
;
Ma, DJ
;
Chao, CJ
;
電子工程學系及電子研究所
We develop an empirical model for the crossover capacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry parameters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance defined on a same layer. The model agrees well with the numerical field solver (with a 6.7% root-mean-square error) and measurement data (with a maximum error of 4.17%) for wire width and spacing down to 0.16 mu m and wire thickness down to 0.15 mu m. The model is useful for VLSI design and process optimization.
An extraction method to determine interconnect parasitic parameters
(1998-11-01)
Chao, CJ
;
Wong, SC
;
Chen, MJ
;
Liew, BK
;
電子工程學系及電子研究所
Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement), In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of a same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer.
An extraction method to determine interconnect parasitic parameters
(1998-11-01)
Chao, CJ
;
Wong, SC
;
Chen, MJ
;
Liew, BK
;
電子工程學系及電子研究所
Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement), In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of a same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer.
An investigation on RF CMOS stability related to bias and scaling
(2002-04-01)
Su, JG
;
Wong, SC
;
Chang, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In recent times, CMOS devices have played an increasing important role in the area of RF-ICs to implement part of the high-frequency circuits. As a result, the high-frequency characteristics of CMOS devices, including stability, should be investigated in-depth. In the design of RF amplifier, the consideration to avoid oscillation in the circuits is a must. Basically, the instability involved in designing RF circuits can be reduced if the transistor is stable in the interesting frequency region. In this study, the stability factor of CMOS device is discussed. First, the stability factor (i.e. k-factor) is derived based on the microwave small-signal model of MOSFET. Therefore, small-signal parameters that affect stability can be carefully examined. In addition, the effects of biasing and dimensions on k-factor are also discussed. Since various operating point (or biasing) can cause device to have different effects on high frequency, the correlation between biasing and stability is discussed in this study. Due to the fact that CMOS device has continuously shrunk in size, a detailed discussion of the effect of MOSFETs dimension on stability is included. It is found from our experimental results that the smaller the gate length, the greater is the frequency range for CMOS device to become potentially unstable. (C) 2002 Elsevier Science Ltd. All rights reserved.
Characterization and Modeling of on-chip inductor substrate coupling effect
(2002)
Chao, CJ
;
Wong, SC
;
Hsu, CJ
;
Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.
Characterization and modeling of on-chip inductor substrate coupling effect
(2002)
Chao, CJ
;
Wong, SC
;
Hsu, CJ
;
Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.
Characterization and Modeling of on-chip inductor substrate coupling effect
(2002-01-01)
Chao, CJ
;
Wong, SC
;
Hsu, CJ
;
Chen, MJ
;
Leu, LY
The substrate coupling effects of two adjacent coplanar spiral inductors are characterized and modeled. The noise magnitude between two 45mum-away inductors can be reduced by 6.83 dB by using guard-ring surrounding each inductor, and improved by 10.28 dB further by adding patterned ground polysilicon shield beneath at 3 GHz. The inductor with patterned polysilicon shield beneath shows improved quality factor and noise isolation. Moreover, a macro model is presented for modeling quality factor and inductance of on-chip spiral inductor and associated neighboring inductor's coupling noise effect.
Characterization and Modeling of on-chip spiral inductors for Si RFICs
(2002-02-01)
Chao, CJ
;
Wong, SC
;
Kao, CH
;
Chen, MJ
;
Leu, LY
The paper presents a complete characterization of on-chip inductors fabricated in BiCMOS technology. First, a study of the scaling effect of inductance on geometry and structure parameters is presented to provide a clear guideline on inductor scaling with suitable quality factors. The substrate noise analysis and noise reduction techniques are then investigated. It is shown that floating well can improve both quality factor and noise elimination by itself under 3 GHz and together with a guard ring above 3 GHz. Finally, for accurate circuit simulations, a new inductor model is developed for predicting the skin effect and eddy effect and associated quality factor and inductance.
Generalized interconnect delay time and crosstalk models: I. Applications of interconnect optimization design
(2001-12-01)
Lee, TGY
;
Tseng, TY
;
Wong, SC
;
Yang, CJ
;
Liang, MS
New analytical models for estimating the delay time of single line and coupled interconnect for ramp input waveform are derived, The accuracy of the signal delay time and crosstalk noise voltage models for various driver resistances, loading capacitances, and input-ramping rates has also been verified by simulation program with integrated circuit emphasis (SPICE) simulation. Based on the delay and crosstalk models, interconnect optimization design can be discussed thoroughly. The proposed guaranteed-performance interconnect design method is also discussed. These models are useful for performance estimation and layout optimization in VLSI synthesis as well as process optimization in technology development.
Generalized interconnect delay time and crosstalk models: II. Crosstalk-induced delay time deterioration and worst crosstalk models
(2001-12-01)
Lee, TGY
;
Tseng, TY
;
Wong, SC
;
Yang, CJ
;
Liang, MS
New analytical models for estimating crosstalk-induced delay time deterioration and the worst crosstalk models of a coupled interconnect for ramp input waveform are derived. The accuracy of these compact models at various driver resistances, loading capacitances, and input-ramping rates is verified by simulation program with integrated circuit emphasis (SPICE) simulation for the parallel interconnect system. The effects of crosstalk noise on the delay time at various ramp input rise times, for both simultaneous and non-simultaneous switching cases, are discussed here. In this study we show that crosstalk noise will be a limiting factor for future fast transition signals. The results reported herein are useful in the studies of delay time uncertainties due to noise and the interconnect worst-case design.
Improving the RF performance of 0.18 mu m CMOS with deep n-well implantation
(2001-10-01)
Su, JG
;
Hsu, HM
;
Wong, SC
;
Chang, CY
;
Huang, TY
The radio-frequency (RF) figures of merit of 0.18 mum complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F-t) and maximum oscillation frequency (F-max). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible dc disturbance. Specifically, 18% increase in F-t and 25% increase in F-max are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications.
Investigations of bulk dynamic threshold-voltage MOSFET with 65GHz "normal-mode" Ft and 220GHz "over-drive mode" Ft for RF applications
(2001)
Chang, CY
;
Su, JG
;
Hsu, HM
;
Wong, SC
;
Huang, TY
The RF properties of bulk dynamic threshold-voltage MOSFET (B-DTMOS) with a deep n-well isolation was investigated both under the normal DTMOS mode and two newly-proposed DTMOS operation modes: moderate (0.6V < Vgs = Vbs < 0.85V) and over-drive (Vgs = Vbs > 0.85V) modes. While Ft can be improved to 65GHz at 12.5mA with 1.5V Vds bias under normal-mode DTMOS operation, a high Ft of 220GHz with good linearity and stability is achieved under over-drive mode of operation.
Modeling of interconnect capacitance, delay, and crosstalk in VLSI
(2000-02-01)
Wong, SC
;
Lee, GY
;
Ma, DJ
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in very large scale integration (VLSI), namely, 1) parallel lines on a plane and 2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson's equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations.
New insights on RF CMOS stability related to bias, scaling, and temperature
(2000)
Su, JG
;
Wong, SC
;
Chang, CY
;
Chiu, KY
;
Huang, TY
The stability issues of CMOS devices for RF applications were studied. The stability factor of MOS devices based on the small-signal model (SSM) parameters was derived, for the first time. The results reveal some new insights on the effects of biasing, and scaling parameters on the stability; and were subsequently confirmed by our experimental results. Our results also show that unconditional stability of RF CMOS devices can be obtained with proper biasing and device geometries. Finally, the effects of temperature on stability were also: investigated. Our results suggest that careful attention needs to be paid for stable low temperature operation.
Pressure boundary treatment in internal gas flows at subsonic speed using the DSMC method
(2001)
Wu, JS
;
Lee, WS
;
Lee, F
;
Wong, SC
;
機械工程學系
Two numerical procedures in the Direct Simulation Monte Carlo method, applying particle flux conservation at inflow/outflow pressure boundaries, are developed to treat the two most important boundary conditions encountered in micromechanical and vacuum devices involving internal gaseous flows. The first one is for both specified pressures at inlet and exit; while the second one is for specified mass flow rate and exit pressure. Both numerical procedures have been tested on short and long micro-channels in the slip and transitional regimes. Excellent agreement has been found between the current results and the previous reported numerical results as well as the experimental data for the first type of boundary conditions. Finally, the first type boundary condition is applied to compute the conductance of flow through a circular pipe to demonstrate its application in vacuum technology. Results compare well with previous experimental data by Knudsen (1909).
Pressure boundary treatment in micromechanical devices using the direct simulation Monte Carlo method
(2001-08-01)
Wu, JS
;
Lee, F
;
Wong, SC
;
機械工程學系
;
Department of Mechanical Engineering
Two numerical procedures in the Direct Simulation Monte Carlo (DSMC) method, applying particle flux conservation at inflow/outflow pressure boundaries, have been developed to treat the two most important boundary conditions encountered in micromechanical devices involving gaseous flows. The first one is for both specified pressures at inlet and exit; while the second one is for specified mass flow rate and exit pressure. Both numerical procedures have been tested on short and long microchannels in the slip and transitional regimes. Excellent agreement has been found between the current results and the previous reported numerical results as well as the experimental data for the first type of boundary conditions. Finally, the developed numerical procedures have been applied to backward-facing micro-step gaseous flows to demonstrate its general applicability in more complicated flows.