Browsing by Author "Wong, Wing Hung"

Now showing 1 - 7 of 7

A 1.86mJ/Gb/Query Bit-Plane Payload Machine Learning Processor in 90nm CMOS
(2018-01-01)
Ku, Fang-Ju
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Wu, Tung-Yu
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Liao, Yen-Chin
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Chang, Hsie-Chia
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Wong, Wing Hung
This paper presents an implementation of an energy efficient hit-plane payload design for machine learning processor. The proposed architecture facilitates high parallelism and high data bandwidth and thus improves the model learning/training time of machine learning algorithms. By assembling multiple bits as a bit-plane and enlarging query parallelism with a central compare-Hag updater, data processing parallelism can be increased. Binary sequential partition (BSP), a fast density estimation algorithm capable of dealing with high dimensional data sets, is realized. Fabricated in 90nm IP9M CMOS process, the processing rate can achieve 16.9 Gb/sec with 8 queries for data dimension D=210. The test chip integrates 64 counting cells and provides 5 modes with power consumptions of 1.86mJ/Gb per Query.
A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications
(2017-10-01)
Tsai, Chang-Hung
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Yu, Wan-Ju
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Wong, Wing Hung
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Lee, Chen-Yi
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電子工程學系及電子研究所
An energy-efficient restricted Boltzmann machine (RBM) processor (RBM-P) supporting on-chip learning and inference is proposed for machine learning and Internet of Things (IoT) applications in this paper. To train a neural network (NN) model, the RBM structure is applied to supervised and unsupervised learning, and a multi-layer NN can be constructed and initialized by stacking multiple RBMs. Featuring NN model reduction for external memory bandwidth saving, low power neuron binarizer (LPNB) with dynamic clock gating and area-efficient NN-like activation function calculators for power reduction, user-defined connection map (UDCM) for both computation time and bandwidth saving, and early stopping (ES) mechanism for learning process, the proposed system integrates 32 RBM cores with maximal 4k neurons per layer and 128 candidates per sample for machine learning applications. Implemented in 65nm CMOS technology, the proposed RBM-P chip costs 2.2 M gates and 128 kB SRAM with 8.8 mm(2) area. Operated at 1.2 V and 210 MHz, this chip achieves 7.53G neuron weights (NWs) and 11.63G NWs per second with 41.3 and 26.7 pJ per NW for learning and inference, respectively.
A 41.3pJ/26.7pJ Per Neuron Weight RBM Processor for on-Chip Learning/Inference Applications
(2016-01-01)
Tsai, Chang-Hung
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YU, Wan-Jun
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Wong, Wing Hung
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Lee, Chen-Yi
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電子工程學系及電子研究所
A restricted Boltzmann machine (RBM) processor (RBM-P) supporting on-chip learning and inference is proposed for machine learning applications in this paper. Featuring neural network (NN) model reduction for external memory bandwidth saving, low power neuron binarizer (LPNB) with dynamic clock gating and area-efficient NN-like activation function calculators, user-defined connection map (UDCM) for both computation time and bandwidth saving, and early stopping (ES) mechanism in learning process, the proposed system integrates 32 RBM cores with maximal 4k neurons per layer and 128 candidates per sample for machine learning applications. Implemented in 65nm CMOS technology', the proposed RBM-P chip costs 2.2M gates and 128kB SRAM with 8.8mm(2) area. Operated at 1.2V and 210MHz, this chip respectively achieves 114.3x and 3.9x faster processing time than CPU and GPGPU. And the proposed RBM-P chip consumes 41.3pJ and 26.7pJ per neuron weight (NW) for learning and inference, respectively.
A Hardware-Efficient Sigmoid Function With Adjustable Precision for a Neural Network System
(2015-11-01)
Tsai, Chang-Hung
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Chih, Yu-Ting
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Wong, Wing Hung
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Lee, Chen-Yi
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電子工程學系及電子研究所
A hardware-efficient sigmoid function calculator with adjustable precision for neural network and deep-learning applications is proposed in this brief. By adopting the bit-plane format of the input and output values, the computational latency of the processing time can be dynamically reduced according to the user configuration. To reduce the hardware cost, the coefficients used to calculate the sigmoid value can be shared for multiple calculators without any structural hazard. In addition, the restricted constraint is applied in the coefficients\' training stage to further simplify the computation in the calculation stage with a negligible quality loss. A test module is designed for the proposal and operated at 300 MHz to achieve 75 million sigmoid calculations per second. Implemented in 90-nm CMOS technology, the core of the calculator costs 1663 gates, and a 1-kb globally shared memory is used to store the coefficients.
CORRELATION-BASED FACE DETECTION FOR RECOGNIZING FACES IN VIDEOS
(2018-01-01)
Hsu, Heng-Wei
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Wu, Tung-Yu
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Wong, Wing Hung
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Lee, Chen-Yi
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電子工程學系及電子研究所
Finding the locations and identities of faces in videos is a very important task in numerous applications. In this paper, we propose a correlation-based face detection approach to improve the performance of face recognition tasks for videos. We apply correlation measures to pairs of response maps which are generated from automatically selected neurons in deep convolutional neural network (CNN) models to detect faces in each video frame. The embeddings extracted from faces cropped by our proposed approach are more consistent across each video sequence and more suitable for face recognition and clustering tasks. Experimental results from the YouTube Faces (YTF) dataset demonstrate that our proposed approach is more robust and achieves better recognition accuracy compared to state-of-the-art face detection approaches.
QuatNet: Quaternion-Based Head Pose Estimation With Multiregression Loss
(2019-04-01)
Hsu, Heng-Wei
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Wu, Tung-Yu
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Wan, Sheng
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Wong, Wing Hung
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Lee, Chen-Yi
Head pose estimation has attracted immense research interest recently, as its inherent information significantly improves the performance of face-related applications such as face alignment and face recognition. In this paper, we conduct an in-depth study of head pose estimation and present a multiregression loss function, an L2 regression loss combined with an ordinal regression loss, to train a convolutional neural network (CNN) that is dedicated to estimating head poses from RGB images without depth information. The ordinal regression loss is utilized to address the nonstationary property observed as the facial features change with respect to different head pose angles and learn robust features. The L2 regression loss leverages these features to provide precise angle predictions for input images. To avoid the ambiguity problem in the commonly used Euler angle representation, we further formulate the head pose estimation problem in quaternions. Our quaternion-based multiregression loss method achieves state-of-the-art performance on the AFLW2000, AFLW test set, and AFW datasets and is closing the gap with methods that utilize depth information on the BIWI dataset.
Towards high performance data analytic on heterogeneous many-core systems: A study on Bayesian Sequential Partitioning
(2018-12-01)
Lai, Bo-Cheng
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Wu, Tung-Yu
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Chiu, Tsou-Han
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Li, Kun-Chun
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Lee, Chia-Ying
Bayesian Sequential Partitioning (BSP) is a statistically effective density estimation method to comprehend the characteristics of a high dimensional data space. The intensive computation of the statistical model and the counting of enormous data have caused serious design challenges for BSP to handle the growing volume of the data. This paper proposes a high performance design of BSP by leveraging a heterogeneous CPU/GPGPU system that consists of a host CPU and a K80 GPGPU. A series of techniques, on both data structures and execution management policies, is implemented to extensively exploit the computation capability of the heterogeneous many-core system and alleviate system bottlenecks. When compared with a parallel design on a high-end CPU, the proposed techniques achieve 48x average runtime enhancement while the maximum speedup can reach 78.76x. (C) 2018 Elsevier Inc. All rights reserved.