Browsing by Author "Wu, Bo-Wei"

Now showing 1 - 8 of 8

A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
;
Li, Kai-Shin
;
Li, Lain-Jong
;
Li, Ming-Yang
;
Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
AlN Surface Passivation of GaN-Based High Electron Mobility Transistors by Plasma-Enhanced Atomic Layer Deposition
(2017-04-27)
Tzou, An-Jye
;
Chu, Kuo-Hsiung
;
Lin, I-Feng
;
Ostreng, Erik
;
Fang, Yung-Sheng
We report a low current collapse GaN-based high electron mobility transistor (HEMT) with an excellent thermal stability at 150 degrees C. The AlN was grown by N-2-based plasma enhanced atomic layer deposition (PEALD) and shown a refractive index of 1.94 at 633 nm of wavelength. Prior to deposit AlN on III-nitrides, the H-2/NH3 plasma pretreatment led to remove the native gallium oxide. The X-ray photoelectron spectroscopy (XPS) spectroscopy confirmed that the native oxide can be effectively decomposed by hydrogen plasma. Following the in situ ALD-AlN passivation, the surface traps can be eliminated and corresponding to a 22.1% of current collapse with quiescent drain bias (V-DSQ) at 40 V. Furthermore, the high temperature measurement exhibited a shift-free threshold voltage (V-th), corresponding to a 40.2% of current collapse at 150 degrees C. The thermal stable HEMT enabled a breakdown voltage (BV) to 687 V at high temperature, promising a good thermal reliability under high power operation.
Corrosion mechanism of annealed equiatomic AlCoCrFeNi tri-phase high-entropy alloy in 0.5 M H2SO4 aerated aqueous solution
(2019-08-15)
Yen, Chao-Chun
;
Lu, Hsueh-Ning
;
Tsai, Ming-Hung
;
Wu, Bo-Wei
;
Lo, Yu-Chieh
This work investigates the corrosion mechanism of annealed equiatomic AlCoCrFeNi tri-phase alloy in 0.5 M H2SO4 aerated aqueous solution. Experimental results indicate that the B2 matrix is preferentially corroded away while grain-boundary FCC and labyrinth-like BCC endure, consistent with the tendency of formation energy for monolayer hydroxide on the (001) plane of three phases calculated by the first principle based on density function theory. Furthermore, the stable passive current density is related to lower k(sp) values of Co(OH)(3), Fe (OH)(3), and Cr(OH)(3), while the annealing effect on enhancing corrosion resistance is owing to the more uniformity of passive hydroxide film.
Hybrid Si/TMD 2D Electronic Double Channels Fabricated Using Solid CVD Few-Layer-MoS2 Stacking for V-th Matching and CMOS-Compatible 3DFETs
(2014)
Chen, Min-Cheng
;
Lin, Chia-Yi
;
Li, Kai-Hsin
;
Li, Lain-Jong
;
Chen, Chang-Hsiao
Stackable 3DFETs such as FinFET using hybrid Si/MoS 2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) I-on,I-n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V-th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.
MOS2 U-shape MOSFET with 10 nm Channel Length and Poly-Si Source/Drain Serving as Seed for Full Wafer CVD MOS2 Availability
(2016)
Li, Kai-Shin
;
Wu, Bo-Wei
;
Li, Lain-Jong
;
Li, Ming-Yang
;
Cheng, Chia-Chin Kevin
A U-shape MOS2 pMOSFET with 10nm channel and poly-Si source/drain is demonstrated. The fabrication process is simple. Because the Si S/D serves as the nucleation seed for CVD MOS2 deposition, thin MOS2 is well deposited in the channel region any where over the fully scale oxide coated Si wafer. This is a big step forward toward a low cost multi-layer stacked TMD IC technology.
Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft
(2018-01-01)
Li, Kai-Shin
;
Wei, Yun-Jie
;
Chen, Yi-Ju
;
Chiu, Wen-Cheng
;
Chen, Hsiu-Chih
In this work, we use thermal-ALD to prepare ferroelectric HfZrO2 (HZO) thin film with thickness from 3 to 7 nm for the NC-FinFET's gate stack. The subthreshold swing (SS) was as low as 5 mV/dec (SSmin) over 4 orders of I-D. Lower thermal budget process, CO2 far-infrared laser activation and 400 degrees C Ni silicide are employed in the 2-level metal backend integration for maintaining the orthorhombic phase in HZO thin film and minimizing the hysteresis in IV. NC-FinFET inverter has 77% higher voltage gain compared to FinFET-inverter employing HfO2 gate dielectric. NC-FinFET ring oscillator exhibit small speed and power advantages over FinFET oscillator. For the first time, NC-FET cut-off frequency (F-t) frequency is measured, 23.1 GHz or 23% higher than the control FET Ft. NC-FinFET SRAM was observed to exhibit large noise margin.
Nonvolatile molecular memory with the multilevel states based on MoS2 nanochannel field effect transistor through tuning gate voltage to control molecular configurations
(2020-04-17)
Lan, Yann-Wen
;
Hong, Chuan-Jie
;
Chen, Po-Chun
;
Lin, Yun-Yan
;
Yang, Chih-Hao
A new flexible memory element is crucial for mobile and wearable electronics. A new concept for memory operation and innovative device structure with new materials is certainly required to address the bottleneck of memory applications now and in the future. We report a new nonvolatile molecular memory with a new operating mechanism based on two-dimensional (2D) material nanochannel field-effect transistors (FETs). The smallest channel length for our 2D material nanochannel FETs was approximately 30 nm. The modified molecular configuration for charge induced in the nanochannel of the MoS2 FET can be tuned by applying an up-gate voltage pulse, which can vary the channel conductance to exhibit memory states. Through controlling the amounts of triggered molecules through either different gate voltage pulses or gate duration time, multilevel states were obtained in the molecular memory. These new molecular memory transistors exhibited an erase/program ratio of more than three orders of current magnitude and high sensitivity, of a few picoamperes, at the current level. Reproducible operation and four-level states with stable retention and endurance were achieved. We believe this prototype device has potential for use in future memory devices.
TMD FinFET with 4 nm Thin Body and Back Gate Control for Future Low Power Technology
(2015)
Chen, Min-Cheng
;
Li, Kai-Shin
;
Li, Lain-Jong
;
Lu, Ang-Yu
;
Li, Ming-Yang
A 4 nm thin transition-metal dichalcogenide (TMD) body FinFET with back gate control is proposed and demonstrated for the first time. The TMD FinFET channel is deposited by CVD. Hydrogen plasma treatment of TMD is employed to lower the series resistance for the first time. The 2 nm thin back gate oxide enables 0.5 V of Vth shift with 1.2 V change in back bias for correcting device variations and dynamically configuring a device as a high performance or low leakage device. TMD can potentially provide sub-nm thin monolayer body needed for 2 nm node FinFET.