Browsing by Author "Wu, CY"

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A 0.8V 5.9GHz wide tuning range cmos VCO using inversion-mode bandswitching varactors
(2005)
Wu, CY
;
Yu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a completely integrated 0.8V 5.9GRz CMOS voltage-controlled oscillator (VCO) with inversion-mode MOS (IMOS) bandswitching varactors. IMOS varactors are used to maintain a large tuning range when the supply voltage is lower than 1V. Moreover, a large resistance connects to the bulk of each IMOS varactor to further improve the VCO tuning capability. Through this large resistance, the tuning range increases by 500MHz. A bandswitching topology is used to ameliorate the adverse effects of highly sensitive IMOS varactors. The VCO was simulated with a 0.8V supply with a tuning range of 29.12% from 4.4 to 5.9 GRz when tuned from 0 to 0.8V. The simulated phase noise is -109.65dBc/Hz at 1MHz offset from the carrier frequency of 5.52GHz. The VCO-core power dissipation is 1.2mW. When the supply is reduced to 0.6V, the tuning range becomes 22.64% from 4.7 to 5.9GHz. The VCO-core dissipates 0.9mW, and the phase noise is -105.24dBc/Hz at 1MHz offset from the carrier frequency of 5.65GHz. The VCO circuit has been designed using TSMC 0.18-mu m CMOS technology with deep n-well processing.
A 1-V 2.4-GHz cmos frequency synthesizer with current-match charge pump
(2004)
Wu, CY
;
Hsieh, CY
;
Chen, WM
;
電機學院
;
College of Electrical and Computer Engineering
A 1-V 2.4-GHz fully integrated frequency synthesizer for Bluetooth applications is proposed and designed in 0.25-mu m CMOS technology. An improved current-match charge pump circuit without the start-up problem is used to reduce the spur level. Moreover, a bandswitching VCO is used to reduce the Kvco and hence the spur level can be further reduced. The prescaler is designed in 1-V supply voltage without the supply-voltage boosting. The circuit is verified by both HSPICE and ADS simulations.
A 1.2 V CMOS four-quadrant analog multiplier
(1997)
Hsiao, SY
;
Wu, CY
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
A new CMOS four-quadrant analog multiplier is proposed and analyzed. By applying differential input signals to a set of combiners, the multiplication function can be implemented. Based on the proposed new combiner circuit, a low-voltage high-performance CMOS four-quadrant analog multiplier is designed and fabricated by 0.8 mu m N-well double-poly-double-metal CMOS technology. Experimental results have shown that, under single 1.2 V supply voltage, the circuit has 0.89% linearity error and 1.1% total harmonic distortion under the maximum-scale input 500 mV(P-P) at both inputs. The measured -3 dB bandwidth is 2.2 MHz and the power dissipation is 2.8 mW. The input bandwidth of the multiplier can be designed to reach the GHz range. Simple structure, low-voltage low-power capability, and high performance make the proposed multiplier quite feasible in many applications.
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
(1998-10-01)
Tseng, YK
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS ((DCB)-B-2-BiCMOS) and differential cross-coupled BiCMOS (DC2-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS; buffer circuit structure is used to achieve high-speed operation under low supply voltage, Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed (DCB)-B-2-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs, HSPICE simulation results have shown that the new (DCB)-B-2-BiCMOS at 1.5 V and the new DC2-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input (DCB)-B-2-BiCMOS XOR/XNOR gate chain fabricated by 0.8-mu m BiCMOS technology that the speed of (DCB)-B-2-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V, Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed (DCB)-B-2-BiCMOS and DC2-BiCMOS logic circuits are feasible for low-voltage, high-speed applications.
A 1.5-V differential cross-coupled bootstrapped BiCMOS logic for low-voltage applications
(1998-10-01)
Tseng, YK
;
Wu, CY
;
交大名義發表
;
電子工程學系及電子研究所
;
National Chiao Tung University
Two new bipolar complementary metal-oxide-semiconductor (BiCMOS) differential logic circuits called differential cross-coupled bootstrapped BiCMOS ((DCB)-B-2-BiCMOS) and differential cross-coupled BiCMOS (DC2-BiCMOS) logic are proposed and analyzed. In the proposed two new logic circuits, the novel cross-coupled BiCMOS; buffer circuit structure is used to achieve high-speed operation under low supply voltage, Moreover, a new bootstrapping technique that uses only one bootstrapping capacitor is adopted in the proposed (DCB)-B-2-BiCMOS logic to achieve fast near-full-swing operation at 1.5 V supply voltage for two differential outputs, HSPICE simulation results have shown that the new (DCB)-B-2-BiCMOS at 1.5 V and the new DC2-BiCMOS logic at 2 V have better speed performance than that of CMOS and other BiCMOS differential logic gates. It has been verified by the measurement results on an experimental chip of three-input (DCB)-B-2-BiCMOS XOR/XNOR gate chain fabricated by 0.8-mu m BiCMOS technology that the speed of (DCB)-B-2-BiCMOS at 1.5 V is about 1.8 times of that of the CMOS logic at 1.5 V, Due to the excellent circuit performance in high-speed, low-voltage operation, the proposed (DCB)-B-2-BiCMOS and DC2-BiCMOS logic circuits are feasible for low-voltage, high-speed applications.
A 1.5V differential cross-coupled bootstrapped BiCMOS logic
(1997)
Tseng, YK
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New full-swing BiCMOS differential logic circuits called differential cross-coupled bootstrapped BiCMOS ((DCB)-B-2-BiCMOS) and differential cross-coupled BiCMOS (DC2-BiCMOS) logic are proposed and analyzed. HSPICE simulations results show that as compared to Bootstrapped BiCMOS CPL logic gate, the new DC2(B)-BiCMOS three-input XOR/XNOR gate with 1.5V supply voltage and 0.5pF output XOR/XNOR gate with 1.5V supply voltage and 0.5pF output loading has about 80% and 86% improvement in the propagation delay and power-delay product, respectively, in 0.8 mu m technology. Moreover, the DC2-BiCMOS with 0.5pF output loading at 2V offers about 57% improvement in the propagation delay time over Pass Transistor BiCMOS (PT-BiCMOS) differential logic gate.
A 1.8GHz CMOS quadrature voltage-controlled oscillator (VCO) using the constant-current LC ring oscillator structure
(1998)
Wu, CY
;
Kao, HS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new fully integrated CMOS quadrature voltage-controlled oscillator (VCO) realized in a standard 0.5 mu m double poly double metal (DPDM) CMOS technology is proposed, that combines a fully differential two-stage ring oscillator with LC tanks and negative resistance to provide both inphase and quadrature output signals. The phase noise is low due to the use of the resonator-type oscillator. The simulation results show that with an on-chip varactor tuned resonator and a control voltage of 0-3 V, the tuning range of the VCO is 160MHz from 1.67GHz to 1.83GHz. Under 1% mismatch of the inductor or capacitor, the phase error of VCO outputs are less than 1 degrees from perfect quadrature and the amplitude ratio are less than 1.0007. The power dissipation is 35mW for 3V power supply. The area is 1.3 x 0.9 mm(2), dominated by the two integrated spiral inductors.
A 2-D velocity- and direction-selective sensor with BJT-based silicon retina and temporal zero-crossing detector
(1999-02-01)
Jiang, HC
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a 2-D velocity- and direction-selective visual motion sensor with a bipolar junction transistor (BJT)-based silicon retina and temporal zero-crossing detector is proposed and implemented. In the proposed sensor, a token-based delay-and-correlate computational algorithm is adopted to detect the selected speed and direction of moving object images. Moreover, binary pulsed signals are used as correlative signals to increase the velocity and direction selectivities, Each basic detection cell in the sensor has a compact architecture, which consists of one BJT-based silicon retina cell, one current-input edge extractor, two delay paths, and four correlators, Using the proposed architecture, an experimental 32 x 32 visual motion sensor chip with a cell size of 100 x 100 mu m(2) has been designed and fabricated by using 0.6-mu m CMOS technology. The correct operations of the fabricated sensor chip have been verified through measurements. The measured ranges of selectively detected velocity and direction in the fabricated sensor chip are 56 mm/s-5 m/s and 0-360 degrees, respectively. The complete sensor system consumes 20 mW at 5 V.
A 2-V low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator and RF amplifier for GHz RF transmitter applications
(2002-02-01)
Wu, CY
;
Kao, HS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A compact low-voltage low-power CMOS direct-conversion quadrature modulator with integrated quadrature voltage-controlled oscillator (VCO) and radio frequency (RF) amplifier for wireless transmitter applications is proposed and analyzed. By applying both baseband input signals with quadrature phases and quadrature local oscillator (LO) signals to a set of combiners, the quadrature modulation functions can be implemented. The low-power operation is enabled by the current reuse technique used among quadrature modulator, quadrature VCO, and RF amplifier. Because only two transistors and one resistor are cascoded in the critical path of the proposed quadrature modulator between power supply and ground, the supply voltage can be as low as 1.5 V. The proposed circuit structure is used to design a quadrature modulator chip for 1.9-GHz digital enhanced cordless telecommunications (DECT) transmitter applications. The experimental chip is fabricated by using 0.35-mum n-well double-poly-triple-metal (DPTM) CMOS technology. The power dissipation is only 18 mW under 2-V power supply voltage. The on-chip quadrature VCO can provide highly accurate quadrature signals without any phase tuning or trimming. The frequency tuning range of the quadrature VCO is 280 MHz from 1.89 to 2.17 GHz at 2-V supply voltage. Due to small mismatch among quadrature signal paths, the measured image ratio is below -42 dBc under 2-V supply voltage when the desired upper side-band (USB) is set at 2 GHz and -51 dBc under 3-V supply voltage when the desired USB at 1.94 GHz. At 2-V supply voltage, the measured LO leakage is -48 dBc. Moreover, the measured second-order intermodulation and third-order intermodulation are less than -46 dBc.
A 5-GHz CMOS double-quadrature receiver for IEEE 802.11a applications
(2003)
Wu, CY
;
Chou, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 5-GHz CMOS double-quadrature front-end receiver for Wireless-LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals and an active polyphase filter is designed to reject image signals. It has the advantages of low power dissipation, small chip area, and low sensitivity to parasitic components. Implemented in 0.18um CMOS technology, the receiver chip can achieve 50.6dB image-rejection with the power dissipation of 22.4mW at 1.8-V voltage supply.
A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator
(2004-03-01)
Wu, CY
;
Chou, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 mum CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.
A CMOS focal-plane retinal sensor designed for shear motion detection
(2004-01-01)
Wu, CY
;
Hsieh, WC
;
Chiang, CT
;
電機學院
;
College of Electrical and Computer Engineering
In this paper, a CMOS focal-plane shear sensor is designed and implemented. The adopted motion computation method is based on correlation-based algorithms with modification to detect the local motion vectors and the adopted retinal processing circuit is to sense and preprocess the incident image. The proposed shear sensor has a shear-motion-like structure to be selective to the direction and velocity of the images. There are totally 76 pixels, which form four shearmotion detection pairs. The area of a single pixel is 52.96 x 55.07 mm 2 with a fill factor of 16%. The chip area is 1151 x 1116 mm 2.
A CMOS focal-plane retinal sensor designed for shear motion detection
(2004-01-01)
Wu, CY
;
Hsieh, WC
;
Chiang, CT
;
電機學院
;
College of Electrical and Computer Engineering
In this paper, a CMOS focal-plane shear sensor is designed and implemented. The adopted motion computation method is based on correlation-based algorithms with modification to detect the local motion vectors and the adopted retinal processing circuit is to sense and preprocess the incident image. The proposed shear sensor has a shear-motion-like structure to be selective to the direction and velocity of the images. There are totally 76 pixels, which form four shearmotion detection pairs. The area of a single pixel is 52.96 x 55.07 mm 2 with a fill factor of 16%. The chip area is 1151 x 1116 mm 2.
A CMOS focal-plane rotation sensor with retinal processing circuit
(2003)
Huang, KH
;
Lin, LJ
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a CMOS focal-plane rotation sensor with the retinal processing circuit is proposed and implemented. The proposed rotation sensor has a polar structure and is selective to the angular velocity and direction (clockwise and counterclockwise) of the rotating images. The selected angular velocity depends on the frequency of an external clock signal, which can be precisely adjusted. In the proposed rotation sensor, there are 104 pixels, which form five concentric circles. The area of a single pixel is 91x84 mum(2) with a fill factor of 20% whereas the chip area is 1812x1825 mum(2). It is found from the experimental results that the detectable angular velocity and illumination range of this rotation sensor are from 2x10(-2) pi/sec to 206 pi/sec as well as from 0.91 lux to 366 lux under a contrast of 80%, respectively.
A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter
(1996-08-01)
Chin, SY
;
Wu, CY
;
電子工程學系及電子研究所
;
電控工程研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes the design of a CMOS capacitor-ratio-independent and gain-insensitive algorithmic analog-to-digital (A/D) converter. Using the fully differential switched-capacitor technique, the A/D converter is insensitive to capacitor-ratio accuracy as well as finite gain and offset voltage of operational amplifiers. The switch-induced error voltage becomes the only major error source, which is further suppressed by the fully differential structure. The proposed A/D converter is designed and fabricated by 0.8 mu m double-poly double-metal CMOS technology. The op-amp gain is only 60 dB and no special layout care is done for capacitor matching. Experimental results have shown that 14-b resolution at the sampling frequency of 10 kHz can be achieved in the fabricated A/D converter. Thus it can be used in the applications which require low-cost high-resolution A/D conversion.
A CMOS ratio-independent and gain-insensitive algorithmic analog-to-digital converter
(1996-08-01)
Chin, SY
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes the design of a CMOS capacitor-ratio-independent and gain-insensitive algorithmic analog-to-digital (A/D) converter. Using the fully differential switched-capacitor technique, the A/D converter is insensitive to capacitor-ratio accuracy as well as finite gain and offset voltage of operational amplifiers. The switch-induced error voltage becomes the only major error source, which is further suppressed by the fully differential structure. The proposed A/D converter is designed and fabricated by 0.8 mu m double-poly double-metal CMOS technology. The op-amp gain is only 60 dB and no special layout care is done for capacitor matching. Experimental results have shown that 14-b resolution at the sampling frequency of 10 kHz can be achieved in the fabricated A/D converter. Thus it can be used in the applications which require low-cost high-resolution A/D conversion.
A compact CMOS 2V low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator and RF amplifier for 1.9GHz RF transmitter applications
(2000)
Kao, HS
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A compact 2V CMOS low-power direct-conversion quadrature modulator merged with quadrature voltage-controlled oscillator (VCO) and RF amplifier for 1.9GHz RF transmitter applications is described. The circuit is implemented by using 0.35 mu m DPTM CMOS technology and dissipates only 19mW under 2V power supply voltage. The low power operation is enabled by the current reuse technique used among quadrature modulator, quadrature VCO, and RF amplifier. Due to small signal path mismatch, the unwanted lower sideband is below -50dB when the 0dB normalized desired upper sideband is set at 1.97GHz. Moreover, the LO feedthrough, second-order intermodulation, and third-order intermodulation are less than -50dB. The tuning range of the quadrature VCO is 270MHz from 1.95GHz to 2.22GHz.
A design strategy for short gate length SOI MESFETs
(1996-03-01)
Hou, CS
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A design strategy for short gate length, self-aligned Si-SOI MESFETs is proposed, in which the design considerations for the important device parameters of the SOI MESFET are studied by using a 2D numerical simulator. It is shown that the sub-threshold I-ds-V-gs characteristics can be used to determine the thickness of silicon film for a given channel doping level under a specified threshold voltage. Moreover, the 2D effect can be suppressed by reducing the thickness of buried oxide to improve the bottom-gate controllability over the channel charges. Moreover, it is shown the backgate bias is also an important controllable parameter for modulating the characteristics of the SOI MESFET in both sub-threshold and saturation regions. An example for designing a very short gate length (0.1 mu m) SOI MESFET has been carried out to verify this strategy. It is shown that the proposed strategy does provide an effective procedure for designing an Si-SOI MESFET with high performance.
A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's
(1997-01-01)
Ker, MD
;
Chang, HH
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMOS IC's without adding an extra ESD-implant mask, Gate-coupling technique is used to couple the ESD-transient voltage to the gates of the PMOS-triggered/NMOS-triggered lateral silicon controlled rectifier (SCR) (PTLSCR/NTLSCR) devices to turn on the lateral SCR devices during an ESD stress, The trigger voltage of gate-coupled lateral SCR devices can be significantly reduced by the coupling capacitor, Thus, the thinner gate oxide of the input buffers in deep-submicron low-voltage CMOS IC's can be fully protected against ESD damage, Experimental results have verified that this proposed ESD protection circuit with a trigger voltage about 7 V can provide 4.8 (3.3) times human-body-model (HBM) [machine-model (MM)] ESD failure levels while occupying 47% of layout area, as compared with a conventional CMOS ESD protection circuit.
A learnable cellular neural network structure with ratio memory for image processing
(2002-12-01)
Wu, CY
;
Cheng, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a learnable cellular neural network (CNN) with space-variant templates and ratio memory (RM) called the RMCNN, is proposed and analyzed. By incorporating both modified Hebbian learning rule and RM into CNN architecture, the RMCNN as the associative memory can generate the absolute weights and then transform them into the ratioed A-template weights as the ratio memories for recognition of noisy input patterns. It is found from simulation results that due to the feature enhancement effect of RM, the RMCNN under constant leakage on template coefficients can store and recognize more patterns than the CNN associative memories without RM, but with the same learning rule and the same constant leakage on space-variant template coefficients. For 9 x 9 (18 x 18) RMCNNs, three (five) patterns can be learned, stored and recognized. Based upon the RMCNN architecture, an experimental chip of CMOS 9 x 9 RMCNN is designed and fabricated by using 0.35 mum CMOS technology. The measurement results have successfully verified the correct functions of RMCNN.