Browsing by Author "Wu, Chien-Hung"

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A novel small planar antenna utilizing cascaded right/left-handed transmission lines
(2007)
Wu, Chien-Hung
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Hsu, Min-Feng
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Wang, Yu-Shin
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Chung, Shyh-Jong
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電信工程研究所
Bias Temperature Instabilities for High-kappa HfO2 LTPS-TFTs With Dual Plasma Treatment
(2016-03)
Wu, Chien-Hung
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Huang, Bo-Wen
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Chang, Kow-Ming
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Chang, Ting-Chia
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Wang, Shui-Jinn
This study is the first to investigate different reliability mechanisms of high-performance low-temperature polycrystalline silicon thin-film transistors (TFTs) with a HfO2 gate dielectric before and after dual plasma treatment (DPT) under various bias temperature instability (BTI) stresses. DPT samples under positive bias temperature instability (PBI) and negative bias temperature instability (NBI) stresses exhibited different degradation phenomena because of the negative polarity trapped oxide charges and positive fixed oxide charges (Si+), respectively. In addition, experimental data exhibited better reliability immunity for PBI stress than NBI stress after DPT. Furthermore, we raised the temperature to clearly observe the effect of the PBTI stress analysis for samples with and without DPT. Extracted measurement results showed distinct time evolutions of the interface state densities (Nit) for samples with and without DPT, revealing the different mechanisms of Nit generation with and without DPT. Finally, we proposed a novel reliability mechanism called the quasi reaction-diffusion model to explain the generation of Delta N-it, which also explains the unclear phenomena of mobility boost.
Characteristics of IGZO TFT Prepared by Atmospheric Pressure Plasma Jet Using PE-ALD Al2O3 Gate Dielectric
(2012-04-01)
Wu, Chien-Hung
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Chang, Kow-Ming
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Huang, Sung-Hung
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Deng, I-Chung
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Wu, Chin-Jyi
This letter proposes a novel atmospheric pressure plasma jet (APPJ) method for indium-gallium-zinc-oxide (IGZO) deposition and use of the plasma-enhanced atomic layer deposition (PE-ALD) Al2O3 as gate dielectric. A nonvacuum and simple APPJ system was demonstrated for channel material deposition. High-transmittance nanocrystalline IGZO thin films were obtained. Excellent electrical characteristics were achieved, including a low V-T of 0.71 V, a small subthreshold swing of 276 mV/dec, a mobility of 8.39 cm(2)/(V . s), and a large I-on/I-off ratio of 1 x 10(8).
Effects of P-Type SnOx Thin-Film Transistors with N-2 and O-2 Ambient Furnace Annealing
(2020-07-01)
Zhang, Yu-Xin
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Wu, Chien-Hung
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Chang, Kow-Ming
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Chen, Yi-Ming
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Xu, Ni
Recently oxide-based thin-film transistors (TFTs) are investigated for emerging applications of the next generation display devices and other electronic circuits (Fortunato, E., et al., 2012. Oxide semiconductor thin-film transistors: A review of recent advances. Advanced Materials, 24, pp.2945-2986). Despite of the great success in n-type oxide semiconductors with high transparency and high field-effect mobility, high performance p-type oxide TFTs are so highly desired that complementary circuits can be realized with low power and high performance (Ou, W.C., et al., 2008. Anomalous p-channel amorphous oxide transistors based on tin oxide and their complementary circuits. Applied Physics Letters, 92, p.122113). There are some oxides such as SnO, CuO, Cu2O and NiO are regarded as promising p-type semiconductor materials. In this investigation, tin oxide SnOx is fabricated to be active layer for TFTs device, and furnace annealing with several combinations of nitrogen and oxygen ambient is compared to enhance the electrical characteristics of p-type SnOx TFTs (Park, K.S., et al., 2009. High performance solution-processed and lithographically patterned zinc-tin oxide thin-film transistors with good operational stability. Electrochemical and Solid-State Lett., 12, pp.H256-H258). The results show that with N-2 + O-2 ambient, 30 minutes furnace annealing, the p-type SnOx TFTs device shows better performance with mobility (mu(FE)) 0.883 cm(2)/V.S, threshold voltage (V-T) -4.63 V, subthreshold swing (SS) 1.15 V/decade, and I-on/I-off ratio 1.01 x 10(3).
Electrical Improvement of MIS Capacitor with HfAlOx Gate Dielectrics Treated by Dual Plasma Treatment
(2012)
Deng, I-Chung
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Chang, Kow-Ming
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Chang, Ting-Chia
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Chang, Po-Chun
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Huang, Bo-Wen
High dielectric constant materials (high-k) such as Hf-based thin films are the promising candidates for 45-nm CMOS technology. It has been described that nitridation processes could improve thermal stability and dielectric constants of Hf-based dielectrics. Furthermore, fluorine incorporation into high-k dielectric was also proposed in order to suppress leakage current and passivate defects. In this study, we examined dual plasma treatment (CF4 pretreatment and N-2 post-treatment) on HfAlOx thin films in order to improve electrical characteristics. Based on our experimental results, HfAlOx Metal-Insulator-Semiconductor (MIS) capacitor properties such as capacitance density, gate leakage current density, and hysteresis could be successfully improved. Compared to untreated samples, capacitance is 42.5% higher and gate leakage is suppressed about three orders when dual plasma treatment is used. According to this study, dual plasma treatment would be an effective technology to improve the electrical characteristic of HfAlOx thin films.
Enhancement of Open-Circuit Voltage Using CF4 Plasma Treatment on Nitric Acid Oxides
(2013-05-01)
Lin, Je-Wei
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Wu, Chien-Hung
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Wu, Sheng-Wei
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Hseih, Wei-Ping
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Du, Chen-Hsu
Surface passivation of solar cells is investigated using CF4 plasma treatment on low-temperature oxides to enhance the open-circuit voltage of the solar cells. Low-temperature oxides grown by a nitric acid solution are treated with the CF4 plasma. Solar cells undergoing this scheme show an improved performance, including low-saturation current density and good quantum efficiency at short wavelengths. Experimental results demonstrate that the CF4 plasma pretreatment on low-temperature oxides can significantly improve the open-circuit voltage, short-circuit current, and fill factor for silicon wafer-based solar cells. This technique is very promising for in-line solar cell manufacturing.
Formation of inverted-pyramid structure by modifying laser processing parameters and acid etching time
(2011)
Lin, Je-Wei
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Liu, En-Ting
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Wu, Chien-Hung
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Hsieh, Ing-Jar
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Chao, Tien-Sheng
This paper is to investigate the possibility to fabricate the inverted-pyramid structure on silicon wafer base solar cell by using laser scribing technology. The UV spectrometer and SEM had also been used to observe the reflectance and microstructure of the wafer surface. In this experiment, a Q-switched Nd:YAG laser operating at wavelength of 1064nm is used to scribe on the p-type wafer surface to produce inverted-pyramid structure. In order to remove the laser damage, we used acid etching and Alkaline etching solutions to smooth the damage region and inverted pyramid structure formed, simultaneously.
High-performance HfO2/ZrO2/IGZO thin-film transistors deposited using atmospheric pressure plasma jet
(2014-11-06)
Wu, Chien-Hung
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Chang, Kow-Ming
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Hsu, Hsin-Yu
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
An atmospheric pressure plasma jet (APPJ) deposition technology that is employed for the preparation of transparent oxide semiconductors film using an eco-friendly water-based metal salt solution as a precursor is presented. Through the use of APPJ indium-gallium-zinc-oxide (IGZO) film as the channel material and a high-k dielectric HfO2/ZrO2 gate stack, IGZO-based transparent thin-film transistors (TFTs) were fabricated and characterised. The HfO2/ZrO2/IGZO-TFTs by APPJ demonstrated excellent electrical characteristics, including a low V-th of 0.63 V, a small subthreshold swing of 0.37 V/dec, a high mobility of 40 cm(2)/V-s and a large I-on/I-off ratio of 7 x 10(8).
Impact of high-k offset spacer in 65-nm node SOI devices
(2007-03-01)
Ma, Ming-Wen
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Wu, Chien-Hung
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Yang, Tsung-Yu
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Kao, Kuo-Hsing
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Wu, Woei-Cherng
In this letter, 65-nm node silicon-on-insulator devices with high-k, offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-k, offset spacer dielectric can effectively increase the ON-state driving current I-ON and reduce the OFF leakage current I-OFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the I-ON/I-OFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-k offset spacer dielectric.
Improvement on Interface Quality and Reliability Properties of HfAlOx MIS Capacitor with Dual Plasma Treatment
(2012)
Chang, Kow-Ming
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Chang, Ting-Chia
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Chang, Po-Chun
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Huang, Bo-Wen
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Wu, Chien-Hung
HfO2 is considered a promising gate dielectric material for sub-45 nm CMOS technology. It has been reported that incorporate Al into HfO2 forming Hf aluminates in order to increase the crystallization temperature. However, the growth of the low-k interfacial layer at high-k/Si interface during high-k dielectric deposition would result in reliability degradation. Recently, incorporating nitrogen into HfAlOx gate dielectrics has beneficial effect on reliability performance. In addition, fluorine incorporation into high-k dielectrics also could have several improvements. In this study, dual plasma (CF4 pre-treatment and N-2 post-treatment) was performed on HfAlOx MIS capacitor in order to improve interface quality and the reliability properties. According to our experimental results, dual plasma treatment could improve interface quality and enhance reliability properties of HfAlOx thin films.
Improving Crystalline Silicon Solar Cell Efficiency Using Graded-Refractive-Index SiON/ZnO Nanostructures
(2015-01-01)
Tu, Yung-Chun
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Wang, Shui-Jinn
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Wu, Chien-Hung
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Chang, Kow-Ming
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Lin, Tseng-Hsing
The fabrication of silicon oxynitride (SiON)/ZnO nanotube (NT) arrays and their application in improving the energy conversion efficiency (eta) of crystalline Si-based solar cells (SCs) are reported. The SiON/ZnO NT arrays have a graded-refractive-index that varies from 3.5 (Si) to 1.9 similar to 2.0 (Si3N4 and ZnO) to 1.72 similar to 1.75 (SiON) to 1 (air). Experimental results show that the use of 0.4 mu m long ZnO NT arrays coated with a 150 nm thick SiON film increases Delta eta/eta by 39.2% under AM 1.5 G (100mW/cm(2)) illumination as compared to that of regular SCs with a Si3N4/micropyramid surface. This enhancement can be attributed to SiON/ZnO NT arrays effectively releasing surface reflection and minimizing Fresnel loss.
Investigation of Electrical Characteristics on AP-PECVD Fabricated Amorphous IGZO TFTs with Hydrogen Plasma Treatment
(2019-04-01)
Wu, Chien-Hung
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Chang, Kow-Ming
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Chen, Yi-Ming
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Zhang, Yu-Xin
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Tan, Yu-Hsuan
TFT panel production process can be divided into three kinds of technology. There have amorphous silicon (a-Si), low-temperature polysilicon (LTPS) and amorphous IGZO (a-IGZO) oxide. Traditional amorphous silicon (a-Si) silicon has a lot of advantages such as good productivity, short process and low-cost. It also has a lot of shortcomings on these applications on TFTs such as photosensitivity, light degradation, and opacity, etc. The dispute of the material based on a-Si: H as an active layer in TFT is low field effect mobility (similar to 1 cm(2)/V.S) (M. Shur and M. Hack, J. Appl. Phys. 55, 3831 (1984)), photo sensitivity (low band gap about 1.7 V) and high deposition temperature (similar to 400 degrees C) (M. Shur, et al., J. Appl. Phys. 66, 3371 (1989); K. khakzar and E. H. Lueder, IEEE Trans. Electron Devices 39, 1438 (1992)). Amorphous In-Ga-Zn-O (IGZO) had attracted attention that compared with the conventional a-Si: H, in the past three years, a-IGZO thin film transistors is more popular which compared with the other oxide semiconductors, because of its larger I-on/I-off ratio (> 10(6)), smaller subthreshold swing (SS), better field-effect mobility and better stability against electrical stress. Hydrogen plasma treatment is applied in improving a-IGZO TFTs active layer, which is fabricated by atmospheric pressure-plasma enhanced chemical vapor deposition (AP-PECVD), the electrical characteristics of a-IGZO TFTs is investigated.
Investigation of Electrical Characteristics on LaAlO3/ZrO2/IGZO TFTs with Microwave Annealing
(2019-04-01)
Wu, Chien-Hung
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Chang, Kow-Ming
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Chen, Yi-Ming
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Zhang, Yu-Xin
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Cheng, Chia-Yao
Conventional thin film transistor suffered from high threshold voltage, poor subthreshold swing, and high operation voltage. These shortcomings make the traditional thin film transistor does not meet the needs with the high-performance, high-resolution, low temperature and energy conservation nowadays. Due to the good selectivity of energy transformation and rapid heating rate, microwave annealing is promising to replace conventional furnace annealing and applied in the investigation. LaAlO3/ZrO2 is employed as gate electrode and gate dielectric layer for a-IGZO TFTs, under the premise that performance of a-IGZO TFTs without decreasing. With adjusting the power/time of microwave annealing, the effect on electrical characteristics of a-IGZO TFTs is investigated.
Investigation of Gate-Stacked In-Ga-Zn-O TFTs with Ga-Zn-O Source/Drain Electrodes by Atmospheric Pressure Plasma-Enhanced Chemical Vapor Deposition
(2018-03-01)
Wu, Chien-Hung
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Chang, Kow-Ming
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Chen, Yi-Ming
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Huang, Bo-Wen
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Zhang, Yu-Xin
Atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) was employed for the fabrication of indium gallium zinc oxide thin-film transistors (IGZO TFTs) with high transparent gallium zinc oxide (GZO) source/drain electrodes. The influence of post-deposition annealing (PDA) temperature on GZO source/drain and device performance was studied. Device with a 300 degrees C annealing demonstrated excellent electrical characteristics with on/off current ratio of 2.13x10(8), saturation mobility of 10 cm(2)/V-s, and low subthreshold swing of 0.2 V/dec. The gate stacked LaAlO3/ZrO2 of AP-IGZO TFTs with highly transparent and conductive AP-GZO source/drain electrode show excellent gate control ability at a low operating voltage.
Investigation of LaAlO3/ZrO2/a-InGaZnO thin-film transistors using atmospheric pressure plasma jet
(2014-04-24)
Wu, Chien-Hung
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Huang, Hau-Yuan
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Wang, Shui-Jinn
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Chang, Kow-Ming
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Hsu, Hsin-Yu
Amorphous indium-gallium-zinc-oxide thin-film transistors (a-IGZO-TFTs) with the LaAlO3/ZrO2 gate dielectric stack employing a novel atmospheric pressure plasma jet process that results in small subthreshold swing and low threshold voltage are proposed and fabricated. The influence of post-deposition annealing (PDA) temperature on LaAlO3/ZrO2 gate dielectric stack and device performance was investigated. The equivalent oxide thickness of the LaAlO3/ZrO2 dielectric stack decreases from 11.5 nm without annealing to 7 nm after a 500 degrees C annealing was applied. The LaAlO3/ZrO2/a-InGaZnO TFT with a 500 degrees C annealing exhibits a small subthreshold swing of 77 mV.dec(-1), a high field-effect mobility of 9 cm(2).V-1.s(-1) and an excellent current ratio of 1.8 x 10(7), which could be attributed to the improved gate dielectric quality by the PDA. The LaAlO3/ZrO2/a-InGaZnO TFTs with excellent gate control ability allow the device to operate at a low operating voltage with low power consumption.
Investigation of Microwave Annealing on Resistive Random Access Memory Device with Atmospheric Pressure Plasma Enhanced Chemical Vapor Deposition Deposited IGZO Layer
(2020-07-01)
Wu, Chien-Hung
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Kuo, Song-Nian
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Chang, Kow-Ming
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Chen, Yi-Ming
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Zhang, Yu-Xin
Non-volatile memory (NVM) is essential in almost every consumer electronic products. The most prevalent NVM used nowadays is flash memory (Meena, J.S., et al., 2014. Overview of emerging nonvolatile memory technologies. Nanoscale Res. Letters, 9(1), p.526). However, some bottlenecks of flash memory have been identified, such as high operation voltage, low operation speed, and poor retention time. Resistive random access memory (RRAM) is considered to be the most promising one to become the next generation NVM device since its simple structure, fast program/erase speed, and low power consumption. In this experiment, the RRAM device is fabricated, and its IGZO (memory) layer is deposited with AP-PECVD technique which can reduce cost of the process. Microwave annealing (MWA) is used to enhance electrical characteristics of the RRAM device (Fuh, C.S., et al., 2011. Role of environmental and annealing conditions on the passivation-free In-Ga-Zn-O TFT. Thin Solid Films, 520, pp.1489-1494). Experiment results show that with appropriate MWA treatment, the IGZO RRAM device exhibits better electrical characteristics under bipolar operation, all forming/set/reset voltage for RRAM device is simultaneously lowered.
Investigation of Microwave Assisted Annealing on AP-PECVD Fabricated In-Ga-Zn-O Thin Film Transistors under Positive Bias Temperature Stress
(2016)
Wu, Chien-Hung
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Huang, Bo-Wen
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Chang, Kow-Ming
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Cheng, Chia-Yao
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Chen, Hsin-Ying
In this paper, microwave assisted annealing (MWAA) technique on atmospheric pressure plasma-enhanced chemical vapor deposition (AP-PECVD) fabricated indium-gallium-zinc-oxide thin-film transistors (IGZO TFTs) is investigated for the first time. MWAA with 300W for 100sec treatment on AP-IGZO TFTs have been fabricated successfully and show excellent electrical characteristics including a VTH of -1.23 V, SS of 0.18 V/dec, mu FE of 17.4 cm2/V-s, and Ion/Ioff ratio of 8.14 106. Stretched exponential time dependence model is used to analyze the mechanism of AP-IGZO TFTs under PBTI stress. Accordingly, chemisorption model for oxygen adsorption at AP-IGZO backchannel with and without MWAA is proposed to explain the mechanism under PBTI stress.
Iridium Nanocrystal Thin-Film Transistor Nonvolatile Memory with Si(3)N(4)/SiO(2) Stack of Asymmetric Tunnel Barrier
(2011-05-01)
Wang, Terry Tai-Jui
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Lu, Tien-Lin
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Wu, Chien-Hung
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Liu, Yu-Cheng
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Hung, Shih-Wei
Iridium nanocrystals (Ir-NCs) lying on the Si(3)N(4)/SiO(2) tunneling layer have been demonstrated and Ir-NC-assisted thin-film transistor nonvolatile memory devices were successfully developed. Results show that Ir-NCs with a number density of similar to 6 x 10(11) cm(-2) and a particle diameter of 4 to 12 nm can successfully be fabricated as charge trapping centers. Owing to the asymmetric SiO(2)/Si(3)N(4) tunneling layer that increases programming/erasing efficiency, a significant memory window of 5.5 V has potential to be applied to multibit memory devices. Furthermore, after 10(4) s, the memory window is still about 4.0 V in logic states. (C) 2011 The Japan Society of Applied Physics
Iridium Nanocrystal Thin-Film Transistor Nonvolatile Memory with Si3N4/SiO2 Stack of Asymmetric Tunnel Barrier
(2011-05-01)
Wang, Terry Tai-Jui
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Lu, Tien-Lin
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Wu, Chien-Hung
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Liu, Yu-Cheng
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Hung, Shih-Wei
Iridium nanocrystals (Ir-NCs) lying on the Si3N4/SiO2 tunneling layer have been demonstrated and Ir-NC-assisted thin-film transistor nonvolatile memory devices were successfully developed. Results show that Ir-NCs with a number density of similar to 6 x 10(11) cm(-2) and a particle diameter of 4 to 12 nm can successfully be fabricated as charge trapping centers. Owing to the asymmetric SiO2/Si3N4 tunneling layer that increases programming/erasing efficiency, a significant memory window of 5.5 V has potential to be applied to multibit memory devices. Furthermore, after 10(4) s, the memory window is still about 4.0 V in logic states. (C) 2011 The Japan Society of Applied Physics
Nickel Nanocrystals Embedded in Metal-Alumina-Nitride-Oxide-Silicon Type Low-Temperature Polycrystalline-Silicon Thin-Film Transistor for Low-Voltage Nonvolatile Memory Application
(2011-06-01)
Wang, Terry Tai-Jui
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Liu, Yu-Cheng
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Wu, Chien-Hung
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Lu, Tien-Lin
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Hsieh, Ing-Jar
In this work, a nickel nanocrystal (Ni-NC) assisted metal-alumina-nitride-oxide-silicon (MANOS) thin-film transistor (TFT) nonvolatile memory (NVM) was fabricated by a standard low temperature polycrystalline silicon (LTPS) TFT process. The size range and density of Ni-NCs were approximately 5-13 nm and 5 x 10(11) cm(-2), respectively. The programming/erasing (P/E) voltages are decreased down to -10 and +8 V, respectively, by the Fowler-Nordheim tunneling mechanism from gate injection. In this P/E voltage condition, a large memory window (similar to 4.2 V) was observed by current-voltage measurement. Then, the speed and voltages of P/E were measured and discussed completely. The data retention of the Ni-NC assisted MANOS-LTPS-TFT-NVM is extracted to be 1.62 V of memory window after 10(4) s. (C) 2011 The Japan Society of Applied Physics