Browsing by Author "Wu, Chien-Ting"

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32-nm Multigate Si-nTFET With Microwave-Annealed Abrupt Junction
(2016-05)
Hou, Fu-Ju
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Sung, Po-Jung
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Hsueh, Fu-Kuo
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Wu, Chien-Ting
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Lee, Yao-Jen
Microwave annealing (MWA) activates dopants through solid-phase epitaxial regrowth with low thermal budget. Optimizing the microwave power during MWA is capable of realizing low defect density at the junction, suppressing the dopant diffusion, and mitigating the straggle effect of ion implantation. These favorable features of MWA facilitate the formation of extremely abrupt junction profiles in tunnel FETs (TFETs). In conjunction with the improved gate-to-channel controllability of the multiple-gate (MG) structure, we demonstrate high-performance lateral n-type Si-TFETs using a CMOS-compatible process flow with excellent band-to-band tunneling efficiency and device scalability. The 32-nm MG Si-TFET shows promising characteristics, including a high ON-state current of 41.3 mu A/mu m, a large current ON/OFF ratio of > 5 x 10(7), and minimal short-channel effect using V-G = 2 V and V-D = 1 V.
A Multi-link Mechanism for Heterogeneous Radio Networks
(2014-06-01)
Yang, Shun-Neng
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Lin, Yung-Chun
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Gan, Chai-Hien
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Lin, Yi-Bing
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Wu, Chien-Ting
Nowadays, smart mobile devices drive the mobile traffic growth rapidly. Most smart mobile devices are equipped with multiple radio network interfaces, such as High Speed Packet Access (HSPA), Long Term Evolution (LTE), and Wi-Fi. Therefore, integration of multiple networks is a viable solution to fulfill traffic offloading and the Quality-of-Service (QoS) requirement of data usage for mobile users. In this paper, we propose a multi-link mechanism to handle the radio network selection and switching between LTE and Wi-Fi networks. A Multi-Link Adaptor (MLA) and a Multi-Connection Manager (MCM) are proposed for the User Equipment (UE) and the core network, respectively, to handle the multi-link mechanism. The applications executed in the UEs do not need to be modified under the proposed approach. The MLA maintains a QoS class table and a routing table for the network selection procedure and uses the GPRS Tunneling Protocol-Control plane (GTP-C) control messages to execute network switching. In the future, we will measure the throughput of the multi-link network and the switch delay between the heterogeneous radio networks.
Characterization of Ultra-Thin Ni Silicide Film by Two-Step Low Temperature Microwave Anneal
(2014)
Wu, Chien-Ting
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Lee, Yao-Jen
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Hsueh, Fu-Kuo
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Sung, Po-Jung
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Cho, Ta-Chun
A novel silicide process with two-step low temperature microwave annealing (MWA) achieves NiSi thickness of 10 nm while maintaining low resistance, and an ultra-thin Ni silicide film, only 4.5 nm, has been realized. In this MWA system, we insert quartz and Si susceptors to change the absorption efficiency of the process wafer and provide fine turning in temperature control during annealing. The thickness of NiSi film is determined by microwave power and by changing the number and the position of quartz and Si susceptors in the first step of the anneal process. The STEM-HAADF combined EELS/EDS spectroscopies are used to analyze the electronic excitations and identify the phase of Ni silicide. (C) 2014 The Electrochemical Society. [DOI: 10.1149/2.006405jss] All rights reserved.
Comparison of 6 Common Noise Filter Methods for Terrestrial Laser Scanner Target
(2012)
Wu, Chien-Ting
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Chen, Ming-Cheng
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土木工程學系
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Department of Civil Engineering
The terrestrial laser scanner (TLS) is a line-of-sight instrument which can directly acquire dense 3D point clouds in a very short time. The registration method is used to act as a control point for a reflective target placed in overlapping areas in neighboring scanning stations. The main purpose for a reflective target is to be an obvious and precise positioning feature for laser scanning point cloud data. This study compares six common noise filtering methods which are used to eliminate measuring noise in the primitive point cloud of reflective target for better positioning accuracy, i.e. Scatter points removal method, Spikes removal method, Least squares plane method, Gaussian smoothing method, Median smoothing method, and the Average smoothing method. The test results found for 30, 60, and 90 meter distances in this study was that six noise filtering methods can actually increase the reflective target positioning accuracy, and the least squares plane method is the best one in either precision or accuracy. Beside the reflective target, the test is carried out with self-made targets for the comparison of positioning accuracy between the reflective target and self-made targets. Regarding accuracy, the reflective target is superior to the object in 30 and 60m, and self-made target is superior to the reflective target in 90m.
Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology
(2015)
Lee, Yao-Jen
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Hou, Fu-Ju
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Chuang, Shang-Shiun
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Hsueh, Fu-Kuo
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Kao, Kuo-Hsing
We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl-2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I-on/I-off ratio exceeding 10(8), the highest ever reported for Ge-based pFETs.
Establishing an invar leveling calibration system
(2008-07-01)
Chen, Chun-Sung
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Wu, Chien-Ting
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Chang, Ming-Wei
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Chang, Wei-Chen
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土木工程學系
Precise height systems are widely utilized in civil engineering projects Such as high-speed railroads, and highways and bridge construction. However, highly precise height data is obtained using precise leveling. An extremely precise invar leveling rod is necessary for obtaining precise results. In this study, an automatic calibration system for invar leveling has been established by the National Measurement Laboratory (NML). The content belongs to the long scales calibration system of D17 of the NML. This system utilizes a steady frequency laser interferometer, a CCD microscopic monitor, and a precise moving mechanism. With this system, an invar rod and a mark invar leveling rod are applied to estimate uncertainty with a 95% confidence level. Uncertainty results are 22 mu m and 21 mu m for the invar leveling rods and mark invar leveling rods, respectively.
Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters
(2020-09-01)
Sung, Po-Jung
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Chang, Shu-Wei
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Kao, Kuo-Hsing
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Wu, Chien-Ting
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Su, Chun-Jung
In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (T-Si) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
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Cho, Ta-Chun
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Sung, Po-Jung
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Kao, Kuo-Hsing
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Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
Identifying the Relationship between GPS Data Quality and Positioning Precision: Case Study on IGS Tracking Stations
(2012-08-01)
Yeh, Ta-Kang
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Chung, Yi-Da
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Wu, Chien-Ting
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Wang, Chuan-Sheng
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Zhang, Kefei
The number of global positioning system (GPS) tracking stations is increasing, primarily because the stations are multifunctional. In civil engineering, they can be used for precision positioning; in the earth sciences, they can be used to monitor faults and earthquakes; and in the atmospheric sciences, they can be applied to predict perceptible water vapor. Currently, there are more than 400 GPS stations in Taiwan; however, the data obtained through such stations are not being assessed carefully. Experienced scientists and engineers examine the data in advance to see if they qualify for research purposes, but inexperienced users can adopt poor quality data that eventually lead to inaccurate research results. Of the observation stations with receivers that were renewed between 2006 and 2008 in the International GNSS Service Network, four stations (ZIMM, BOR1, NRC1, and NICO) were selected to be the subjects of this research. Six indexes of data quality were observed to calculate the quality of data obtained before and after receiver renewal. Then, analyses were conducted to understand the relationship between the quality indexes and positioning precision. The results showed that after receiver renewal, the positioning precision of the four stations was improved by 1-19%. Therefore, positioning precision is positively affected by the six data quality indexes. It was also discovered that receiver clock error was the most critical factor among the six indexes. In conclusion, if data quality control can be applied to GPS tracking stations, the data obtained will be more reliable for research purposes, and the accuracy of subsequent engineering and science measurements will be improved. DOI: 10.1061/(ASCE)SU.1943-5428.0000077. (C) 2012 American Society of Civil Engineers.
Improving Handover and Drop-off Performance on High-Speed Trains With Multi-RAT
(2014-12-01)
Lin, Yi-Bing
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Yang, Shun-Neng
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Wu, Chien-Ting
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資訊學院
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資訊工程學系
Provisioning commercial mobile telecommunications service on a high-speed train (HST) faces several challenges. In particular, when an HST quickly passes through the radio coverage of the base stations, frequent handovers may result in serious communication interruption. Methods such as the hierarchical two-hop network and the seamless dual-link handover scheme were proposed to address these challenges. This paper proposes the multiple radio access technology (multi-RAT) to resolve the HST handover issue, which allows the HST to simultaneously connect to two or more heterogeneous mobile networks (e.g., the Universal Mobile Telecommunications System and Long Term Evolution). With this approach, the handover process can be improved by keeping multiple heterogeneous network links of the HST at the same time and maintaining the connection through one link during the handover process of the other link. We show that multi-RAT can effectively enhance HST communications by reducing the impact of handover failure. This approach can work together with other solutions such as the dual-link scheme to further enhance the performance of the HST communications.
Large-Area 2D Layered MoTe2 by Physical Vapor Deposition and Solid-Phase Crystallization in a Tellurium-Free Atmosphere
(2017-09-08)
Huang, Jyun-Hong
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Deng, Kuang-Ying
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Liu, Pang-Shiuan
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Wu, Chien-Ting
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Chou, Cheng-Tung
Molybdenum ditelluride (MoTe2) has attracted considerable interest for nanoelectronic, optoelectronic, spintronic, and valleytronic applications because of its modest band gap, high field-effect mobility, large spin-orbit-coupling splitting, and tunable 1T/2H phases. However, synthesizing large-area, high-quality MoTe2 remains challenging. The complicated design of gas-phase reactant transport and reaction for chemical vapor deposition or tellurization is nontrivial because of the weak bonding energy between Mo and Te. This study reports a new method for depositing MoTe2 that entails using physical vapor deposition followed by a postannealing process in a Te-free atmosphere. Both Mo and Te are physically deposited onto the substrate by sputtering a MoTe2 target. A composite SiO2 capping layer is designed to prevent Te sublimation during the postannealing process. The postannealing process facilitates 1T-to-2H phase transition and solid-phase crystallization, leading to the formation of high-crystallinity few-layer 2H-MoTe2 with a field-effect mobility of approximate to 10 cm(2) V-1 s(-1), the highest among all nonexfoliated 2H-MoTe2 currently reported. Furthermore, 2H-MoS2 and Td-WTe2 can be deposited using similar methods. Requiring no transfer or chemical reaction of metal and chalcogen reactants in the gas phase, the proposed method is potentially a general yet simple approach for depositing a wide variety of large-area, high-quality, 2D layered structures.
Large-area few-layer MoS2 deposited by sputtering
(2016-06)
Huang, Jyun-Hong
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Chen, Hsing-Hung
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Liu, Pang-Shiuan
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Lu, Li-Syuan
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Wu, Chien-Ting
Direct magnetron sputtering of transition metal dichalcogenide targets is proposed as a new approach for depositing large-area two-dimensional layered materials. Bilayer to few-layer MoS2 deposited by magnetron sputtering followed by post-deposition annealing shows superior area scalability over 20 cm(2) and layer-by-layer controllability. High crystallinity of layered MoS2 was confirmed by Raman, photo-luminescence, and transmission electron microscopy analysis. The sputtering temperature and annealing ambience were found to play an important role in the film quality. The top-gate field-effect transistor by using the layered MoS2 channel shows typical n-type characteristics with a current on/off ratio of approximately 10(4). The relatively low mobility is attributed to the small grain size of 0.1-1 mu m with a trap charge density in grain boundaries of the order of 10(13) cm(-2).
Monitoring of Sag Deformation in Suspension Bridges Using a 3D Laser Scanner
(2010-12-01)
Chen, Ming Cheng
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Chen, Chun-Sung
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Wu, Chien-Ting
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Wang, Edward H.
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土木工程學系
This study discusses the causes of main cable sag damage on suspension bridges Although the cable extension caused by the sag is not apparent, it has some important characteristics One such characteristic is that the cable, being hyperbolic, contains a central region that is strictly level If an average of points was taken along this central region, inspection accuracy could be increased With changes in sag, the damage to the cable can be estimated Three-dimensional (3D) scanners can accurately obtain the cloud points from the main cable of the suspension bridge in real time and in the long term This, along with visual testing (VT), can be used to verify the study The results obtained through laboratory and field experimentation in this study were close to the expected theoretical results
Monolithic 3D SRAM-CIM Macro Fabricated with BEOL Gate-All-Around MOSFETs
(2019-01-01)
Hsueh, Fu-Kuo
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Lee, Chun-Ying
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Xue, Cheng-Xin
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Shen, Chang-Hong
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Shieh, Jia-Min
For the first time, below 400 degrees C-fabricated gate-all-around (GAA) transistor fabrication process was demonstrated with monolithic computing-in-memory (CIM) circuit. Key enablers are plasma-assisted atomic layer etching (PA-ALE), plasma immersion ion implantation (PIII) and far-infrared laser activation (FIR-LA). The 3D stackable single-grained Si GAA MOSFETs thus fabricated exhibit record-high I-on/I-off ratio (similar to 10(8)) with low I-off (pFETs<10(-2) nA/mu m). Moreover, the stackability of the GAA MOSFETs and the differential output of dual-mode 10T SRAM readout enable 2x throughput in the CIM circuitry.
MOS2 U-shape MOSFET with 10 nm Channel Length and Poly-Si Source/Drain Serving as Seed for Full Wafer CVD MOS2 Availability
(2016)
Li, Kai-Shin
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Wu, Bo-Wei
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Li, Lain-Jong
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Li, Ming-Yang
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Cheng, Chia-Chin Kevin
A U-shape MOS2 pMOSFET with 10nm channel and poly-Si source/drain is demonstrated. The fabrication process is simple. Because the Si S/D serves as the nucleation seed for CVD MOS2 deposition, thin MOS2 is well deposited in the channel region any where over the fully scale oxide coated Si wafer. This is a big step forward toward a low cost multi-layer stacked TMD IC technology.
Suspended Diamond-Shaped Nanowire With Four {111} Facets for High-Performance Ge Gate-All-Around FETs
(2016-10)
Hou, Fu-Ju
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Sung, Po-Jung
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Hsueh, Fu-Kuo
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Wu, Chien-Ting
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Lee, Yao-Jen
A feasible pathway to scale germanium (Ge) FETs in future technology nodes has been proposed using the tunable diamond-shaped Ge nanowire (NW). The Ge NW was obtained through a simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The different etching selectivity of surface orientations for Cl-2 and HBr was employed for the three-step isotropic/anisotropic/isotropic dry etching. The ratio of Cl-2 and HBr, mask width, and Ge recess depth were crucial for forming the nearly defect-free suspended Ge channel through effective removal of dislocations near the Si/Ge interface. This technique could also be applied for forming diamond-shaped Si NWs. The suspended diamond-shaped NW gate-all-around NWFETs feature excellent electrostatics, the favorable {111} surfaces along the < 110 > direction with high carrier mobility, and the nearly defect-free Ge channel. The pFET with a high I-ON/I-OFF ratio of 6 x 10(7) and promising nFET performance have been demonstrated successfully.