Browsing by Author "Wu, Chun-Yu"

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A New Charge-Trap-Engineered Memory Device with Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) Structure for LTPS-TFT-Based Applications
(2010)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chen, Sheng-Kai
;
Yu, Ming H.
;
Kang, Tsung-Kuei
For the first time, a new Silicon-Oxide-Nitride-Vacuum-Silicon (SONVAS) LTPS-TFT-based charge-trapping memory integrated on a gate-all-around field-enhanced-nanowire architecture was demonstrated. The vacuum, simply formed by an in-situ encapsulation, substituted for the traditional tunneling oxide. Due to the lowest-k and empty properties of vacuum, SONVAS features electric field enhancement in tunneling layer and immunity against the creation of interface traps and the charge trapping in the damaged tunneling oxide during P/E cycling, resulting in the much-improved P/E efficiency and reliability, respectively. Therefore, such vacuum-introduced SONVAS memory device with process simplicity is very suitable for the future system-on-panel (SOP) and 3D-stacking flash applications.
A Novel LTPS-TFT-Based Charge-Trapping Memory Device with Field-Enhanced Nanowire Structure
(2009)
Liao, Ta-Chuan
;
Chen, Sheng-Kai
;
Yu, Ming H.
;
Wu, Chun-Yu
;
Kang, Tsung-Kuei
A novel gate-all-around low-temperature poly-Si (LIPS) thin-film transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory with field-enhanced nanowire (FEN) structure has been proposed to improve the program and erase (P/E) performance. Each nanowire inherently had three sharp corners fabricated simply by sidewall spacer formation to obtain high local electric fields. The field-enhanced carrier tunneling via such a structure led to faster PIE speed and wider memory window for the FEN-TFT SONOS as compared to the conventional planar (CP) counterpart. The improvement was also further verified with the simulation results. Such a high-performance FEN-TFT SONOS memory with process simplicity is very suitable for future system-on-panel (SOP) applications.
A Novel Polysilicon Field-Enhanced Nanowire Thin-Film Transistor with the TiN-Hafnia-Nitride-Vacuum-Silicon (THNVAS) Structure for Nonvolatile Memory Applications
(2012-07-01)
Wu, Chun-Yu
;
Liao, Ta-Chuan
;
Liu, Yen-Ting
;
Yu, Ming H.
;
Cheng, Huang-Chung
A novel poly-Si field-enhanced nanowire (FEN) TFT memory with the TiN-hafnia-nitride-vacuum-silicon (THNVAS) structure fabricated simply via a sidewall spacer formation has been presented. The THNVAS devices with superior memory performance were demonstrated by introducing the hafnia as blocking oxide and the vacuum, the lowest-k in nature, as tunneling layer. According to the simulation results, the memory device with oxide/nitride/vacuum gate dielectric exhibited a higher local electric-field of 4.72 x 10(7) V/cm as compared to 2.55 x 10(7) V/cm for the conventional oxide/nitride/oxide counterpart. In addition, the electric-field of tunneling layer could be further increased to 7.06 x 10(7) V/cm while the blocking oxide was substituted for hafnia. The experimental data showed that THNVAS possessed a greater threshold voltage shift of 3.75 V in 10 ms at V-GS = 12 V, whereas the shift only 2.5 V for THNOS ones. These considerable improvements for THNVAS devices could be attributed to the evident field enhancement across the vacuum tunneling layer. Furthermore, owing to the empty feature of vacuum tunneling layer, the THNVAS demonstrated much-improved endurance performance and preferable data retention property. Hence, such excellent characteristics of THNVAS will be an attractive nonvolatile memory for future system-on-panel and 3-D Flash applications.
A novel self-aligned field induced drain polycrystalline silicon thin film transistor fabricated by using a selective side etch process
(2007)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chien, Feng-Tso
;
Tsai, Chun-Chien
;
Chen, Hsiu-Hsin
A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with vacuum gaps has been proposed and fabricated only with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. Experimental results reveal that the proposed T-Gate poly-Si TFTs have excellent electrical performance, which has maximum on-off current ratio of 4.6 x 10(7), and off-state leakage current at V-GS = -10 V and V-DS = 5V of about 100 times less than that of the conventional one. These improvements are attributed to the additional undoped offset region and the vacuum gap, which reduce the maximum electric field at drain junction while the sub-gate maintains the on-current. Therefore, such a T-Gate poly-Si TFT is very suitable for the applications and manufacturing in active matrix liquid crystal displays (AMLCDs) and active matrix organic light emitting diodes (AMOLEDs).
A poly-Si thin-film transistor with the in situ vacuum gaps under the T-shaped-gated electrode
(2006)
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Chien, Feng-Tso
;
Tsai, Chun-Chien
;
Chen, Hsiu-Hsin
A T-shaped-gated (T-gate) poly-Si thin-film transistor (TFT) with symmetric vacuum gaps has been proposed and fabricated simply with a selective-etching technique and an in situ vacuum encapsulation. The proposed TFT has demonstrated a higher maximum on-off current ratio and superior reliability compared to the conventional TFTs. This is attributed to the resulting offset region and vacuum gap to reduce the off-state leakage current and improve the hot-carrier reliability, while the extra subgate serves to induce an inversion layer at the offset region to maintain the on current during the on state. Therefore, such a T-gate poly-Si TFT is very suitable for manufacturing and applications in active-matrix flat panel electronics. (c) 2006 The Electrochemical Society.
Comparison of Multiple-Polysilicon-Nanowire pH-Sensors Coated with Different ALD-Deposited High-k Dielectric Materials
(2011)
Hsu, Po-Yen
;
Wu, Chun-Yu
;
Cheng, Huang-Chung
;
Wu, You-Lin
;
Chang, Wei-Tzu
Multiple poly-silicon nanowires (PS-NW\'s) coated with different high-k dielectric materials, HfO2, Al2O3, and TiO2, were fabricated and their pH sensing characteristics were compared. Sidewall spacer formation technique was used for the PS-NW\'s fabrication and all the high-k materials were deposited by atomic-layer-deposition (ALD). Following the high-k dielectric deposition, a 3-aminopropyltriethoxysilane (gamma-APTES) layer was coated as sensing membrane. It is found that the multiple PS-NW sensor coated with HfO2 exhibits the highest sensitivity and best reproducibility for pH sensing.
Effects of crystallization mechanism on the electrical characteristics of green continuous-wave-laser-crystallized polycrystalline silicon thin film transistors
(2013-07-29)
Chou, Chia-Hsin
;
Lee, I-Che
;
Yang, Po-Yu
;
Hu, Ming-Jhe
;
Wang, Chao-Lung
Thin film transistors (TFTs) with amorphous silicon films crystallized via continuous-wave green laser at a wavelength of 532 nm exhibit very different electrical characteristics in various crystallization regions, corresponding to the Gaussian energy density distribution of the laser beam. In the center region subjected to the highest energy density, the full melting scheme led to the best crystallinity of the polycrystalline silicon film, resulting in the highest field-effect mobility of 500 cm(2) V-1 s(-1). In contrast, the edge region that resulted in solid phase crystallization exhibited the worst mobility of 48 cm 2 V-1 s(-1) for the polycrystalline silicon TFTs. (C) 2013 AIP Publishing LLC.
Field enhancement of omega-shaped-gated poly-Si TFT SONOS memory fabricated by a simple sidewall spacer formation
(2010-05-01)
Wu, Chun-Yu
;
Liao, Ta-Chuan
;
Yu, Ming-H
;
Chen, Sheng-Kai
;
Tsai, Chung-Min
A novel omega-shaped-gated (Omega-Gate) poly-Si thin-film-transistor (TFT) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices fabricated with a simple process have been proposed for the first time. The Omega-Gate structure inherently covered two sharp corners manufactured simply via a side-wall spacer formation. Due to the sharp corner geometry, the local electric fields across the tunneling oxide could be enhanced effectively, thus improving the memory performance. Based on this field enhanced scheme, the Omega-Gate TFT SONOS revealed excellent program/erase (P/E) efficiency and larger memory window as compared to the conventional planar (CP) counterparts. In addition, owing to the better gate controllability, the Omega-Gate TFT SONOS also exhibited superior transistor performance with a much higher on-current, smaller threshold voltage, and steeper subthreshold swing. Therefore, such an Omega-Gate TFT SONOS memory is very promising for the embedded flash on the system-on-panel applications. (C) 2010 Elsevier Ltd. All rights reserved.
Gate-all-around polycrystalline-silicon thin-film transistors with self-aligned grain-growth nanowire channels
(2012-02-27)
Liao, Ta-Chuan
;
Kang, Tsung-Kuei
;
Lin, Chia-Min
;
Wu, Chun-Yu
;
Cheng, Huang-Chung
In this letter, gate-all-around (GAA) polycrystalline silicon thin-film transistors (TFTs) with self-aligned grain-growth channels were fabricated using excimer laser crystallization (ELC) on a recessed-nanowire (RN) structure. Via the RN structure constructed by a simple sidewall-spacer formation, location-controlled nucleation and volume-confined lateral grain growth within the RN body during ELC process have been demonstrated with only one perpendicular grain boundary in each nanowire channel. Because of the high-crystallinity channel together with GAA operation mode, the proposed GAA-RN TFTs show good device integrity of lower threshold voltage, steeper subthreshold slope, and higher field-effect mobility as compared with the conventional planar counterparts. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3691184]
High Sensitivity of Dry-Type Nanowire Sensors With High-k Dielectrics for pH Detection via Capillary Atomic Force Microscope Tip Coating Technique
(2012-09-01)
Cheng, Huang-Chung
;
Wu, Chun-Yu
;
Hsu, Po-Yen
;
Wang, Chao-Lung
;
Liao, Ta-Chuan
Dry-type poly-Si nanowire pH sensors with high-k dielectrics have been demonstrated with the aid of novel focus ion beam engineered capillary atomic force microscopy (C-AFM) tip. By means of this C-AFM tip coating technique, the relatively few testing solutions can be transferred onto the surface of a nanowire, preventing the sensor device from the immersion in the liquid and therefore suppressing the possible leakage current from the testing solution. As compared with the TEOS SiO2, the pH sensors comprising Al2O3, TiO2, and HfO2 high-k materials exhibit the better sensitivities due to their enhanced capacitances. The best sensitivity (138.7 nA/pH) and linearity (99.69%) for a HfO2 dielectric can be ascribed to the higher k value and larger bandgap with respect to the Al2O3 and TiO2, accordingly. Consequently, the C-AFM tip coating technique incorporating with HfO2 dielectric suggests the potential for the detection of a minute quantity of biomedicines.
High-Performance Excimer-Laser-Crystallized Polycrystalline Silicon Thin-Film Transistors with the Pre-Patterned Recessed Channel
(2012-06-01)
Wang, Chao-Lung
;
Cheng, Huang-Chung
;
Lee, I-Che
;
Wu, Chun-Yu
;
Cheng, Yu-Ting
High-performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) have been achieved using an excimer laser crystallization method on a prepatterned recessed channel (RC). Such a prepatterned RC TFT exhibited an excellent field-effect mobility of 412 cm(2) V-1 s(-1) and an on/off current ratio higher than 1:1 x 10(8) as compared with 125 cm(2) V-1 s(-1) and 2:2 x 10(7) for the conventional ones, respectively. This is attributed to the two-dimensional control of the grain boundary location and the resultant cross-shaped grain boundary structures within the recessed regions. Therefore, the prepatterned RC TFTs with only one grain boundary parallel to the channel direction as the TFTs could be fabricated to avoid the perpendicular grain boundary. This technology is thus promising for the future applications of poly-Si TFTs in the system-on-panel (SOP) and three-dimensional integrated circuits (3D-ICs). (C) 2012 The Japan Society of Applied Physics
High-performance polycrystalline silicon thin-film transistors prepared via the laser crystallization of the prepatterned channel layer on the bottom-gate structure
(2013-02-01)
Wang, Chao-Lung
;
Lee, I-Che
;
Wu, Chun-Yu
;
Cheng, Yu-Ting
;
Yang, Po-Yu
High-performance polycrystalline silicon thin-film transistors (TFTs) using an excimer laser crystallization of the prepatterned channel layer on the bottom-gate (BG) structure were fabricated to exhibit a field-effect mobility as high as 339 cm(2)/V s and an on/off current ratio of 9.5x10(7) with respect to 102 cm(2)/V s and 1.5x10(7) for the conventional top-gate (TG) TFTs, respectively. Such a superior performance is attributed to the cross-shaped grain boundary structure formed in the channel region owing to the two-dimensional location control of grain boundaries. Moreover, the prepatterned BG TFTs show better device-to-device uniformity than the conventional TG ones due to the manipulated grain boundaries. This technology is thus promising for the future applications of system-on-panel and three-dimension integrated circuits. (C) 2012 Elsevier B.V. All rights reserved.
High-Performance Polycrystalline Silicon Thin-Film Transistors with Two-Dimensional Location Control of the Grain Boundary via Excimer Laser Crystallization
(2012-07-01)
Wang, Chao-Lung
;
Lee, I-Che
;
Wu, Chun-Yu
;
Liao, Chan-Yu
;
Cheng, Yu-Ting
High-performance low-temperature polycrystalline silicon (Poly-Si) thin-film transistors (TFTs) have been fabricated with two-dimensional (2-D) location-controlled grain boundaries using excimer laser crystallization (ELC). By locally increased thickness of the amorphous silicon (a-Si) film that was served as the seed crystals with a partial-melting crystallization scheme, the cross-shaped grain boundary structures were produced between the thicker a-Si grids. The Poly-Si TFTs with one parallel and one perpendicular grain boundary along the channel direction could therefore be fabricated to reach excellent field-effect mobility of 530 cm(2)/V-s while the conventional ones exhibited field-effect mobility of 198 cm(2)/V-s. Furthermore, the proposed TFTs achieved not only superior electric properties but also improved uniformity as compared with the conventional ones owing to the artificially controlled locations of grain boundaries.
High-Performance Polycrystalline-Silicon Nanowire Thin-Film Transistors With Location-Controlled Grain Boundary via Excimer Laser Crystallization
(2012-11-01)
Wang, Chao-Lung
;
Lee, I-Che
;
Wu, Chun-Yu
;
Chou, Chia-Hsin
;
Yang, Po-Yu
High-performance polycrystalline-silicon (poly-Si) nanowire (NW) thin-film transistors (TFTs) are demonstrated using excimer laser crystallization to control the locations of grain boundaries two-dimensionally. Via the locally increased thickness of the amorphous-silicon (a-Si) film as the seeds, the cross-shaped grain boundary structures were produced among these thicker a-Si grids. The NW TFTs with one primary grain boundary perpendicular to the channel direction could be therefore fabricated to achieve an excellent field-effect mobility of 346 cm(2)/V . s and an on/off current ratio of 3 x 10(9). Furthermore, the grain-boundary-location-controlled NW TFTs also exhibited better reliability due to the control of grain boundary locations. This technology is thus promising for applications of low-temperature poly-Si TFTs in system-on-panel and 3-D integrated circuits.
High-Performance Single-Crystal-Like Strained-Silicon Nanowire Thin-Film Transistors via Continuous-Wave Laser Crystallization
(2015-04-01)
Chou, Chia-Hsin
;
Chan, Wei-Sheng
;
Lee, I-Che
;
Wang, Chao-Lung
;
Wu, Chun-Yu
High-performance polycrystalline-silicon nanowire (NW) thin-film transistors (TFTs) have been demonstrated via continuous-wave laser crystallization (CLC) to exhibit the low subthreshold swing of 216 mV/decade and high ON/OFF ratio of 1.6x10(9). In addition, the thermal stress of similar to 800 MPa induced from the CLC process also contributed to the single-crystal-like silicon NW CLC TFTs to achieve an excellent field-effect mobility of up to 900 cm(2)V(-1)s(-1).
Improving electrical performance of the scaled low-temperature poly-Si thin film transistors using vacuum encapsulation technique
(2008)
Lin, Wei-Kai
;
Liao, Ta-Chuan
;
Wu, Chun-Yu
;
Tu, Shih-Wei
;
Liu, Yen-Ting
A novel T-shaped-gated (T-Gate) polycrystalline silicon thin-film transistor (poly-Si TFT) with in-situ vacuum gaps has been proposed and fabricated with a simple process. The T-Gate structure is formed only by a selective undercut-etching technology of the Mo/Al bi-layers. Then, vacuum gaps are in-situ embedded in this T-Gate structure subsequent to capping the SiH4-based passivation oxide under the vacuum process chamber. The proposed T-Gate poly-Si TFT has demonstrated to suppress the short-channel effects by simulated and measured characterization. It is attributed to the undoped offset region and vacuum gap to reduce the maximum electric field at drain Junction..
Novel Dielectric-Engineered Trapping-Charge Poly-Si-TFT Memory With a TiN-Alumina-Nitride-Vacuum-Silicon Structure
(2011-08-01)
Wu, Chun-Yu
;
Liu, Yen-Ting
;
Liao, Ta-Chuan
;
Yu, Ming H.
;
Cheng, Huang-Chung
High-performance poly-Si-TFT-based TiN-alumina-nitride-vacuum-silicon (TANVAS) trapping-charge memory has been demonstrated utilizing high-k blocking oxide and vacuum tunneling layer for the first time. In particular, the vacuum, lowest k in nature, was introduced to replace the traditional tunneling oxide. Furthermore, the alumina high-k blocking oxide was applied to upgrade the electric field across the tunneling layer. Based on the enlarged k-value difference between the blocking and tunneling layers, the TANVAS featured considerable field enhancement across the tunneling layer, thus much improving the program/erase efficiencies. In addition, owing to the suppression of defect creation in the tunneling layer, the TANVAS also exhibited superior retention characteristics. These excellent memory characteristics of TANVAS are therefore promising for the 3-D Flash and system-on-panel applications.
Novel junctionless silicon-oxide-nitride-oxide-silicon memory devices with field-enhanced poly-Si nanowire structure
(2015-08-01)
Chou, Chia-Hsin
;
Chan, Wei-Sheng
;
Wu, Chun-Yu
;
Lee, I-Che
;
Liao, Ta-Chuan
In this work, a novel gate-all-around (GAA) low-temperature poly-Si (LTPS) junctionless (JL) silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory device with a field-enhanced nanowire (NW) structure has been proposed to improve the programing/erasing (P/E) performance. Each nanowire has three sharp corners fabricated by a sidewall spacer formation technique to obtain high local electrical fields. Owing to the higher carrier concentration in the channel and the high local electrical field from the three sharp corners, such a JL SONOS memory device exhibits a significantly enhanced P/E speed, a larger memory window, and better data retention properties than a conventional inversion mode NW-channel memory device. (C) 2015 The Japan Society of Applied Physics
Polysilicon Nanowire Sensor Devices Based on High-k Dielectric Membrane for pH Sensing and DNA Detection
(2012)
Wu, Chun-Yu
;
Hsu, Po-Yen
;
Wang, Chao-Lung
;
Liao, Ta-Chuan
;
Cheng, Huang-Chung
The pH sensing characteristics of poly-Si nanowires with high-k sensing membranes are investigated. As a result, the sensing membrane of HfO2 exhibits higher sensitivity and better reproducibility test as compared with TEOS SiO2, Al2O3, TiO2 films. The sensor device with HfO2 dielectric membrane reveals a great pH sensitivity of 172.8 nA/pH. In additon, the label-free DNA detection ability of the poly-Si nanowires is also demonstrated. The 10-base-long single-strained homopolymers DNA molecule solution with an ultra-low concentration of 0.01nM can be detected by using HfO2 sensing film. Such a poly-Si nanowires structure with HfO2 sensing membrane is very suitable for future biochemical sensors applications.
Reliability improvement of InGaZnO thin film transistors encapsulated under nitrogen ambient
(2012-04-09)
Wu, Chun-Yu
;
Cheng, Huang-Chung
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Wang, Chao-Lung
;
Liao, Ta-Chuan
;
Chiu, Po-Chun
The nitrogen ambient encapsulation (NAE) technique is introduced to improve the reliability issue for the amorphous InGaZnO (a-IGZO) thin-film transistors under positive gate bias stress (PGBS). For the NAE devices, the threshold voltage (Vth) shift is significantly decreased from 1.88 to 0.09 V and the reduction of saturation drain current is improved from 15.75 to 5.61 mu A as compared to the bare a-IGZO counterparts after PGBS. These improvements are attributed to the suppression of negatively charged oxygen adsorption on the a-IGZO backsurface and thereby well maintain the channel potential of NAE devices, which in turn sustain the Vth during PGBS. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3702794]