Browsing by Author "Wu, Chung-Cheng"

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A constant-mobility method to enable MOSFET series-resistance extraction
(2007-12-01)
Lin, Da-Wen
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Cheng, Ming-Lung
;
Wang, Shyh-Wei
;
Wu, Chung-Cheng
;
Chen, Ming-Jer
A new method of extracting the MOSFET series resistance R-sd is proposed. This method requires only simple dc measurements on a single test device. Experimental demonstration is presented, without requiring quantities such as gate-oxide thickness, physical gate length, or effective channel length. The merit of the method stems from the specifically arranged bias conditions in which the channel carrier mobility remains constant for high vertical electric fields. It is this unique property which, makes the proposed method suitable for short-channel devices.
A millisecond-anneal-assisted selective fully silicided (FUSI) gate process
(2008-09-01)
Lin, Da-Wen
;
Wang, Maureen
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Cheng, Ming-Lung
;
Sheu, Yi-Ming
;
Tarng, Bennet
We demonstrate, for the first time, an integration-friendly selective PMOSFET fully silicided (FUSI) gate process. In this process, a millisecond-anneal (NISA) technique is utilized for the nickel silicide phase transformation. A highly tensile FUSI gate electrode is created and hence exerts compressive stress in the underlying channel. The highly flexible integration scheme successfully, and exclusively, implements uniform P+ FUSI gates for PMOSFETs while preserving a FUSI-free N+ poly-Si gate for PMOSFETs with the feature size down to 30 run. A 20% improvement in FUSI-gated PMOSFET I-on-I-off is measured, which can be attributed to the enhanced hole mobility and the elimination of P+ poly-gate depletion.
A Novel Method of MOSFET Series Resistance Extraction Featuring Constant Mobility Criteria and Mobility Universality
(2010-04-01)
Lin, Da-Wen
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Cheng, Ming-Lung
;
Wang, Shyh-Wei
;
Wu, Chung-Cheng
;
Chen, Ming-Jer
A method of MOSFET series resistance extraction is established in this paper. The core of this method relies on the constant mobility criteria, while for different gate lengths, it preserves the shape of universal mobility curves in the high-vertical-field regime. Consequently, the series resistance of a MOSFET can be extracted in an analytical and self-consistent manner, achieved without the knowledge of the gate oxide thickness, channel length, channel doping, or channel stress. Reasonable values of extracted series resistance are demonstrated in a wide range of gate length. Technology computer-aided design simulation further corroborates the validity of the proposed method, particularly for devices with heavily doped source/drain extensions. The constant mobility criteria with respect to the bulk charge linearization coefficient are also verified.
An Extreme Surface Proximity Push for Embedded SiGe in pMOSFETs Featuring Self-Aligned Silicon Reflow
(2010-09-01)
Lin, Da-Wen
;
Chen, Chien-Liang
;
Chen, Ming-Jer
;
Wu, Chung-Cheng
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電子工程學系及電子研究所
This letter proposes a novel process to modulate the distance, or proximity, between the tip of embedded silicon-germanium (e-SiGe) and the channel region in pMOSFETs. Traditionally, sophisticated etching treatment is adopted in a spacer structure; however, process-induced variation in the e-SiGe proximity may lead to serious variation in pMOSFET performance. In this letter, an extremely close proximity is achieved using self-aligned silicon reflow (SASR) in hydrogen ambient. As opposed to conventional approaches which have e-SiGe proximity determined by spacer width, the tip of e-SiGe with SASR can be positioned flush with the gate edge, as corroborated by both the TEM analyses and TCAD simulation. A significant improvement in pMOSFET performance is also measured.
Process Integration and Interconnection Design of Passive-Matrix LED Micro-Displays With 256 Pixel-Per-Inch Resolution
(2020-01-01)
Yuan, Shuo-Huang
;
Yan, Shih-Siang
;
Yao, Yu-Shiuan
;
Wu, Chung-Cheng
;
Horng, Ray-Hua
A 0.28-inch InGaN-based blue micro-LED display with 256 pixel-per-inch resolution and a pitch of $100 mu m was successfully fabricated in this study. A thick Ti/Al/Ti/Au interconnection metal was deposited on the n-type gallium nitride (n-GaN) region to reduce the interconnection resistance. The micro-LED array with interconnection metal exhibits better electrical property consistency as compared with that of the traditional one. The output power, forward voltage, and external quantum efficiency of micro-LED, which measured under 1-mA current injection with the full lighting mode, are 0.8 mW, 3.0 V, and 10%, respectively. This technique has the potential to integrate InGaN-based LEDs with quantum dots for full-color applications.