Browsing by Author "Wu, Chung-Shiang"

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A 50 nW-to-10 mW Output Power Tri-Mode Digital Buck Converter With Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting
(2016-02)
Chen, Po-Hung
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Wu, Chung-Shiang
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Lin, Kai-Chun
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交大名義發表
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National Chiao Tung University
This paper presents a tri-mode digital buck converter in 0.18-mu m CMOS technology for photovoltaic energy harvesting. The on-chip gate-boosted digital pulsewidth modulation (DPWM) improves the conversion efficiency at heavy load conditions. Pulse-frequency modulation (PFM) along with digital self-tracking zero current detection is proposed to avoid reverse current at light load. The asynchronous mode (AM) operation further reduces the controller loss and improves the conversion efficiency at ultra-light load conditions. By applying DPWM, PFM, and AM at different load conditions, the proposed converter provides a maximum conversion efficiency of 92% with output power ranging from 50 nW to 10 mW. In addition, the proposed buck converter achieves more than 70% efficiency from 400 nW to 10 mW output power.
A 50nW-to-10mW Output Power Tri-Mode Digital Buck Converter with Self-Tracking Zero Current Detection for Photovoltaic Energy Harvesting
(2015-01-01)
Chen, Po-Hung
;
Wu, Chung-Shiang
;
Lin, Kai-Chun
;
交大名義發表
;
National Chiao Tung University
All Digitally Controlled Linear Voltage Regulator with PMOS Strength Self-Calibration for Ripple Reduction
(2015)
Kuo, Yi-Ping
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Huang, Po-Tsang
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Wu, Chung-Shiang
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Liang, Yu-Jie
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Chuang, Ching-Te
In this paper, an all-digitally controlled linear voltage regulator is proposed for ultra-low-power event-driven sensing platforms using a PMOS strength self-calibration technique. The voltage regulator generates the output voltage from 0.43V to 0.55V in steps of 30mV with a supply voltage of 0.6V. Against PVT and loading current variations, the PMOS strength self-calibration circuitry utilizes a voltage-detected coarse tune and a timing-detected fine tune for output ripple reduction. The coarse tune is designed to suppress the output voltage within the fine-tune region via a comparator-based error detector. Accordingly, the fine tune block detects the PMOS turn-on ratio in a specific time window for further reducing the output ripple. This linear voltage regulator is implemented using TSMC 65nm LP CMOS process. The simulation results show the best improvement of ripple reduction by 81%. Moreover, ns-order voltage transition time and the best ( lowest) FOM of 0.76 pA.s can be realized.
An All-Digital Power Management Unit with 90% Power Efficiency and ns-order Voltage Transition Time for DVS Operation in Low Power Sensing SoC Applications
(2015)
Wu, Chung-Shiang
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Lin, Kai-Chun
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Kuo, Yi-Ping
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Chen, Po-Hung
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Chu, Yuan-Hua
A 1V similar to 1.2V battery input, 0.4V similar to 0.6V output low-power all-digital power management unit (PMU) composed of a high-efficiency digital buck converter (DBC) and a fast-transient digital low drop-out (DLDO) regulator is developed for energy-efficient SoC applications. A fully integrated 2-to-1 switchedcapacitor dc-dc converter is combined together to reduce the quiescent current of digital control circuits. The digital pulse width modulation (DPWM) with clock frequency gating further reduces the power consumption of buck converter in steady state. From experiment results, the peak power efficiency of the proposed buck converter is 90% with an output power range of 30 mu W to 3mW and the peak current efficiency of DLDO is 98.8% at 5mW. Moreover, the proposed DLDO achieves 92ns/ 130ns transition time in 60mV voltage step to dynamically scaling the voltage of supply voltage in digital circuits. This chip is designed and fabricated in 65nm CMOS process for verification.
Digital Buck Converter With Switching Loss Reduction Scheme for Light Load Efficiency Enhancement
(2017-02)
Wu, Chung-Shiang
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Lee, Hui-Hsuan
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Chen, Po-Hung
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Hwang, Wei
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電子工程學系及電子研究所
In this brief, we present a digital pulsewidth modulation buck converter with a switching loss reduction scheme to improve conversion efficiency at light load conditions. The proposed switching loss reduction scheme combines power-stage voltage swing scaling, transistor width scaling, and controller voltage scaling to reduce the dynamic power dissipation of the system. The power-stage voltage swing scaling also reduces the inductor current ripple at light load conditions, which extends the available output current range in the continuous conduction mode (CCM). A duty ratio estimation mechanism is implemented to provide a modulated signal with the correct duty ratio to control the output voltage. Experimental results demonstrate a 38% conversion efficiency improvement at a 50-mu A output current. In addition, the proposed circuit achieves a 96% peak efficiency with an output current ranging from 20 mu A to 30 mA in the CCM operation.