Browsing by Author "Wu, DY"

Now showing 1 - 4 of 4

A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxide
(2002)
Chung, SS
;
Chen, SJ
;
Yang, CK
;
Cheng, SM
;
Lin, SH
For the first time, an improved charge pumping (CP) method has been implemented for direct determination of the interface traps in ultra-short gate length CMOS devices with ultra-thin gate oxide in the direct tunneling regime. The leakage current in a 12-16A gate oxide can be removed from the measured CP current, which enables accurate determination of the interface traps. This method has, been demonstrated successfully for various RTNO grown and RPN treated oxide CMOS devices with very thin gate oxide. Moreover, it can be used as a good monitor of ultra-thin gate oxide process and the evaluations of device reliabilities in relating to the interface trap generation.
Comparison of oxide breakdown progression in ultra-thin oxide SOI and bulk pMOSFETs
(2004)
Chan, CT
;
Kuo, CH
;
Tang, CJ
;
Chen, MC
;
Wang, TH
Accelerated oxide breakdown progression in ultra-thin oxide (1.4nm) SOI pMOSFETs is observed, as compared to bulk devices. The accelerated progression is explained by the increase of hole stress current as a result of breakdown induced channel carrier heating in a floating-body configuration. Numerical simulation of hole tunneling current and hot carrier luminescence measurement are carried out to justify the proposed theory.
Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range
(2004)
Chung, SS
;
Feng, HJ
;
Hsieh, YS
;
Liu, A
;
Lin, WM
A low leakage characterization technique for the lateral profiling of interface and oxide traps in a 12Angstrom-16Angstrom range gate oxide CMOS devices has been demonstrated. The approach being taken includes an incremental frequency Charge-Pumping(IFCP) measurement and a neutralization procedure such that interface and oxide traps can be separated. The most critical steps are the elimination of leakage current during measurement and a neutralization procedure, which enables accurate detennination of interface and oxide traps. This method has been demonstrated successfully for an advanced sub-100nm CMOS devices. As an important merit for its application, evaluations of HC reliability and NBTI effect have also been demonstrated. Evaluations of gate oxide qualities with plasma nitridation in both n- and p-MOSFET reliabilities have been properly described based on the current analysis technique.
Negative substrate bias enhanced breakdown hardness in ultra-thin oxide pMOSFETs
(2003)
Wang, TH
;
Tsai, CW
;
Chen, MC
;
Chan, CT
;
Chiang, HK
Negative substrate bias enhanced breakdown hardness in ultra-thin oxide (1.4nm) pMOS is observed. This result is believed due to the increase of hole stress current during breakdown progression via breakdown induced carrier heating. Numerical analysis of substrate bias effect on hole tunneling current is performed to support the proposed theory. This phenomenon is particularly significant to gate oxide reliability in floating substrate (PD-SOI) or forward-biased substrate devices.