Browsing by Author "Wu, Di-You"

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A Grouped-Iterative Framework for MIMO Detection
(2008)
Wu, Di-You
;
Van, Lan-Da
;
資訊工程學系
;
Department of Computer Science
In this paper, we propose one grouped-iterative framework to generate a family of the MIMO detection algorithms. The presented framework not only includes the conventional iterative, grouped, and Chase detection algorithms, but also derives a new low-complexity MIMO detection algorithm. The proposed detection can adjust some parameters to achieve a range of trade-offs between performance and complexity. In (4,4) system with uncoded 16-QAM inputs, one instance of the proposed detection algorithm not only substantially reduces the multiplication complexity by 26.3% but also outperforms the BODF algorithm about 5dB. Another instance of the proposed algorithm can save multiplication complexity by 34% at the penalty of 1 dB loss compared with the B-Chase detector.
Efficient Detection Algorithms for MIMO Communication Systems
(2011-03-01)
Wu, Di-You
;
Van, Lan-Da
;
資訊工程學系
;
Department of Computer Science
In this paper, two new efficient detection algorithms, Type 1 (T1) with better complexity-performance tradeoff and Type 2 (T2) with lower complexity, are derived from one generalized framework for multiple-input multiple-output (MIMO) communication systems. The proposed generalized detection framework constructed by parallel interference cancellation (PIC), group, and iteration techniques provides three parameters and three sub-algorithms to generate two efficient detection algorithms and conventional BLAST-ordered decision feedback (BODF), grouped, iterative, and B-Chase detection algorithms. Since the group interference suppression (GIS) technique is applied to the proposed detection algorithms, the complexities of the preprocessing (PP) and tree search (TS) can be reduced. In (8,8) system with uncoded 16-QAM inputs, one example of the T1 algorithm can save complexity by 21.2% at the penalty of 0.6 dB loss compared with the B-Chase detector. The T2 algorithm not only reduces complexity by 21.9% but also outperforms the BODF algorithm by 3.1 dB.
Energy-Efficient FastICA Implementation for Biomedical Signal Separation
(2011-11-01)
Lan-Da Van
;
Wu, Di-You
;
Chen, Chien-Shiun
;
資訊工程學系
;
Department of Computer Science
This paper presents an energy-efficient fast independent component analysis (FastICA) implementation with an early determination scheme for eight-channel electroencephalogram (EEG) signal separation. The main contributions are as follows: 1) energy-efficient FastICA using the proposed early determination scheme and the corresponding architecture; 2) cost-effective FastICA using the proposed preprocessing unit architecture with one coordinate rotation digital computer-based eigenvalue decomposition processor and the proposed one-unit architecture with the hardware reuse scheme; and 3) low-computation-time FastICA using the four parallel one-units architecture. The resulting power dissipation of the FastICA implementation for eight-channel EEG signal separation is 16.35 mW at 100 MHz at 1.0 V. Compared with the design without early determination, the proposed FastICA architecture implemented in united microelectronics corporation 90 nm 1P9M complementary metal-oxide-semiconductor process with a core area of 1.221 x 1.218 mm(2) can achieve average energy reduction by 47.63%. From the post-layout simulation results, the maximum computation time is 0.29 s.