Browsing by Author "Wu, Guo-Wei"

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A 3.125 Gbps CMOS fully integrated optical receiver with adaptive analog equalizer
(2007)
Chen, Wei-Zen
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Huang, Shih-Hao
;
Wu, Guo-Wei
;
Liu, Chuan-Chang
;
Huang, Yang-Tung
This paper presents the design of a 3.125 Gbps monolithic CMOS optical receiver, integrating a photo detector, a transimpedance amplifier, and a post limiting amplifier on a single chip. The optical receiver is capable of delivering 420 mV(PP) to 50 Omega output load after optical to electrical conversion. High speed operation is achieved by utilizing spatial modulated light (SML) detector and adaptive analog equalizer. Implemented in a 0.18 mu m CMOS technology, the total power dissipation is 175 mW. The chip size is 0.7 mm(2).
An 8 Gbps Fast-Locked Automatic Gain Control for PAM Receiver
(2009)
Wu, Guo-Wei
;
Chen, Wei-Zen
;
Huang, Shih-Hao
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An 8 Gbps automatic gain control (AGC) loop for PAM receiver is proposed. Incorporating digital intensive gain control scheme, the dynamic range of the variable gain amplifier is 22 dB with a resolution of 0.9 dB/step. The locking time of the AGC loop is less than 200 ns and independent of input amplitude. Fabricated in a 0.18 mu m CMOS technology, the chip size is 0.62 mm x 0.62 mm. The total power dissipation is 84 mW from a 1.8 V supply.