Browsing by Author "Wu, Hsin-Han"

Now showing 1 - 2 of 2

Evaluation of the thermal conductance of flip-chip bonding structure utilizing the measurement based on Fourier's law of heat conduction at steady-state
(2018-06-01)
Wu, Chia-Yu
;
Huang, Yin-Hsien
;
Wu, Hsin-Han
;
Hsieh, Tsung-Eong
;
材料科學與工程學系
Fourier's law of heat conduction at steady-state was adopted to establish a measurement method utilizing platinum (Pt) thin-film electrodes as the heater and the temperature sensor. The thermal conductivities (kappa's) of Pyrex glass, an epoxy resin and a commercial underfill for flip-chip devices were measured and a good agreement with previously reported values was obtained. The thermal boundary resistances (R-TBR 's) of Pt/sample interfaces were also extracted for discussing their influence on the thermal conduction of samples. Afterward, the flip-chip samples with 2x2 solder joint array utilizing Si wafers as the die and the substrate, without and with the underfills, were prepared and their thermal conductance were measured. For the sample without underfill, the air presenting in the gap of die and the substrate led to the poor thermal conductance of sample. With the insertion of underfills, the thermal conductance of flip-chip samples improved. The resistance to heat transfer across Si/underfill interfaces was also suppressed and to promote the thermal conductance of samples. The thermal properties of underfill and R-TBR at Si/underfill interface were further implanted in the calculation of thermal conductance of flip-chip samples containing various solder joint arrays. The increasing number of solder joints diminished the influence of thermal conduction of underfill and R-TBR of Si/underfill interface on the thermal conductance of samples. The insertion of underfill with high-kappa value might promote the heat conductance of samples containing low-density solder joint arrays; however, it became insignificant in improving the heat conductance of samples containing high-density solder joint arrays. (C) 2018 Author(s).
Forming-free, bi-directional polarity conductive-bridge memory devices with Ge2Sb2Te5 solid-state electrolyte and Ag active electrode
(2015-01-07)
Huang, Yin-Hsien
;
Chen, Hsuan-An
;
Wu, Hsin-Han
;
Hsieh, Tsung-Eong
;
材料科學與工程學系
Preparation and characteristics of conductive-bridge random access memory devices containing Ge2Sb2Te5 (GST) chalcogenide as the solid-state electrolyte, Ag as the active electrode, and W-Ti as the counter electrode are presented. As revealed by the electrical measurement, only the samples containing crystalline GST exhibited the resistive switching behaviors. With an insertion of ZnS-SiO2 dielectric layer at the Ag/GST interface and a postannealing at 100 degrees C for 1 min, the sample exhibited the best electrical performance with satisfactory cycleability and retention properties. Moreover, the forming-free and bi-directional polarity features were observed in such a sample type. Microstructure and composition analyses found the finely dispersed nano-scale Ag clusters in GST and, when electrical bias is applied, the migrating Ag ions may build up the connections in between neighboring Ag clusters. Moreover, grain boundaries in polycrystalline GST might be the main paths for Ag migration. The thread-like conduction channels in GST hence form, leading to the low resistance state of sample. On the contrary, the depletion of Ag in GST broke the connections in between Ag clusters when the electrical bias is reversed. This led to the rupture of conduction channels and, hence, the high resistance state of sample. The low operational voltage, forming-free, and bi-directional polarity features observed in (AZGW)(T) sample might also originated from the fine dispersion of Ag clusters in GST electrolyte. (C) 2015 AIP Publishing LLC.