Browsing by Author "Wu, I-Wei"

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Area-Efficient Instruction Set Extension Exploration with Hardware Design Space Exploration
(2011-09-01)
Wu, I-Wei
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Chung, Chung-Ping
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
Instruction set extension (ISE) is an effective approach to improve the processor performance without tremendous modification in its core architecture. To execute ISE(s), a processor core must be augmented with a new functional unit, called application specific functional unit (ASFU), which consists of multiple hardware implementation options of ISEs (ISE_HW). Obviously, since ISE_HW increases the production cost of a processor core, minimizing the area size of ISE_HW becomes important for ISE exploration. On the other hand, because of different requirements in space and speed, ISE_HW usually has multiple hardware implementation options. Under pipeline-stage timing constrain:, some of these options may have the same performance improvement but entail different hardware costs. According to this phenomenon, the area size of ISE_HW can be reduced by performing hardware design space exploration of ISE_HW. Therefore, in this paper, we propose an ISE exploration algorithm that explores not only ISE but also the hardware design space of ISE_HW. Compared with the previous research, our approach resulted in significant improvement in area efficiency and the execution performance.
Dynamic Memory Optimization and Parallelism Management for OpenCL
(2014-01-01)
Hsu, Chao-Hung
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Wu, I-Wei
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
Recently, multiprocessor platforms have become trends for achieving high performance. OpenCL (Open Computing Language) is one of the programming standards for heterogeneous multiprocessors, and provides portability for these platforms. Our research focuses on platforms with CPUs and GPUs since GPUs are now widespread in use. On such a platform, two programming issues may affect the performance on GPU computing significantly. One is the work load distribution and another is the employment of GPU memory hierarchy. To fully utilize the characteristics of GPUs, programmers have to be not only proficient at parallel programming but also familiar with hardware specifications. Therefore, in this paper, we propose a compilation pass to automatically perform optimizations for OpenCL kernels. Our compilation pass will transform an input naive kernel function with optimizations, including kernel function analysis, work- group rearrangement, memory coalescing, and work-item merge. In addition, our framework is implemented on a runtime system so that it may dynamically adjust the optimizing parameters according to the hardware specifications. Considering the execution time, the optimized kernels generated by our design may have significant performance improvement over the naive versions. Although the optimizations performed in runtime may incur time overheads, the overheads may be covered by intensive kernel computation or massive input data in most cases.
ETAHM: An energy-aware task allocation algorithm for heterogeneous multiprocessor
(2008)
Chang, Po-Chun
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Wu, I-Wei
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Shann, Jyh-Jiun
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Chung, Chung-Ping
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資訊工程學系
In demand of more computing power and less energy use, multiprocessor with power management facility emerges in embedded system design recently. Dynamic Voltage Scaling is such a facility that varies clock speed and supply voltage to save more energy. In this paper, we propose ETAHM to allocate tasks on a target multiprocessor system. In pursuit of global optimal solution, it mixes task scheduling, mapping and DVS utilization in one phase and couples ant colony optimization algorithm. Extensive experiments show ETAHM could save 22.71% more energy than CASPER [1], a state-of-the-art integrated framework that tackles the identical problem with genetic algorithm instead.
Extended Instruction Exploration for Multiple-Issue Architectures
(2014-11-01)
Wu, I-Wei
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Shann, Jean Jyh-Jiun
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Hsu, Wei-Chung
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Chung, Chung-Ping
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交大名義發表
In order to satisfy the growing demand for high-performance computing in modern embedded devices, several architectural and microarchitectural enhancements have been implemented in processor architectures. Extended instruction (EI) is often used for architectural enhancement, while issuing multiple instructions is a common approach for microarchitectural enhancement. The impact of combining both of these approaches in the same design is not well understood. While previous studies have shown that EI can potentially improve performance in some applications on certain multiple-issue architectures, the algorithms used to identify EI for multiple-issue architectures yield only limited performance improvement. This is because not all arithmetic operations are suited for EI for multiple-issue architectures. To explore the full potential of EI for multiple-issue architectures, two important factors need to be considered: (1) the execution performance of an application is dominated by critical (located on the critical path) and highly resource-contentious (i.e., having a high probability of being delayed during execution due to hardware resource limitations) operations, and (2) an operation may become critical and/or highly resource contentious after some operations are added to the EI. This article presents an EI exploration algorithm for multiple-issue architectures that focuses on these two factors. Simulation results show that the proposed algorithm outperforms previously published algorithms.
Improving Performance of JNA by Using LLVM JIT Compiler
(2013)
Tsai, Yu-Hsin
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Wu, I-Wei
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Liu, I-Chun
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Shann, Jean Jyh-Jiun
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資訊工程學系
Java Native Access (JNA) has been proposed to alleviate the burden of programming in Java Native Interface (JNI). JNA allows programmer to call native functions without writing any JNI codes. However, JNA suffers from some performance degradation. To overcome this problem, in this paper, we modify the JNA source code and integrate the LLVM JIT compiler into JNA to improve the performance. Our experiment achieves about 8% to 16% performance improvement for calling a native function with different types and numbers of arguments. Furthermore, our design is a non-traditional way of using the runtime compiler, and the challenges we encountered may help other researchers to face the similar situations.
Instruction Emulation and OS Supports of a Hybrid Binary Translator for x86 Instruction Set Architecture
(2015-01-01)
Liu, I-Chun
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Wu, I-Wei
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Shann, Jean Jyh-Jiun
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資訊工程學系
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Department of Computer Science
Binary translation is one of the most important techniques of virtualization. The main purpose of a binary translator (BT) is to translate an executable from a source instruction set architecture (ISA) to a target ISA. Traditionally, there are two types of binary translators: static binary translator (SBT) and dynamic binary translator (DBT). In recent years, a new type of BT called hybrid binary translator (HBT) was proposed, which translates the source executable first at static time, and then, at run time, if the execution of the target executable emits an exception because of reaching statically untranslated code, it switches to the attached dynamic translator for translating these code. Therefore, an HBT may have the merits of both good performance of SBT and easy handling of code discovery and code location problems of DBT. Nowadays, massive application programs have been developed for x86 platforms, and thus, many binary translators have been proposed for x86 ISA. However, due to the characteristics of CISC architecture of x86, for example, variable-length instruction format, the BT designed for it previously usually apply dynamic translation strategy or make use of profiling data for resolving the code discovery and code location problems. In this paper, we present an HBT which supports x86 ISA and emulates the execution behavior of an x86 executable under Linux operation system. In our x86-32 to x86-64 translation experiments, the target executables translated by our HBT outperform that of QEMU on most programs of EEMBC benchmark suite.
Instruction set extension exploration in multiple-issue architecture
(2008)
Wu, I-Wei
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Chen, Zhi-Yuan
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Shann, Jyh-Jiun
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Chung, Chung-Ping
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資訊工程學系
To satisfy high-performance computing demand in modern embedded devices, current embedded processor architectures provide designer with possibility either to define customized instruction set extension (ISE) or to increase instruction issue width. Previous studies have shown that deploying ISE in multiple-issue architecture can significantly improve performance. However, identifying ISE for multiple-issue architecture by using current ISE exploration algorithms will result in unnecessary waste of silicon area and limitation of performance improvement. This is because most algorithms overlook two important considerations: (1) only packing the operations lying on the critical path into ISE can improve performance; (2) the critical path usually changes after packing operations into an ISE. With these considerations, this paper presents an algorithm for ISE exploration based on list scheduling and Ant Colony Optimization (ACO), in which combines ISE exploration and the critical path identification (i.e. instruction scheduling). Results indicate that our approach outperforms the previous work in both performance improvement and area efficiency.
Instruction set extension generation with considering physical constraints
(2007)
Wu, I-Wei
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Huang, Shih-Chia
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Chung, Chung-Ping
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Shann, Jyh-Jiun
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資訊工程學系
In this paper, we propose new algorithms for both ISE exploration and selection with considering important physical constraints such as pipestage timing and instruction set architecture (ISA) format, silicon area and register file. To handle these considerations, an ISE exploration algorithm is proposed. It not only explores ISE candidates but also their implementation option to minimize the execution time meanwhile using less silicon area. In ISE selection, many researches only take silicon area into account, but it is not comprehensive. In this paper, we formulate ISE selection as a multiconstrained 0-1 knapsack problem so that it can consider multiple constraints. Results with MiBench indicate that under same number of ISE, our approach achieves 69.43%, 1.26% and 33.8% (max., min. and avg., respectively) of further reduction in silicon area and also has maximally 1.6% performance improvement compared with the previous one.
Reconfigurable Custom Functional Unit Generation and Exploitation for Multiple-Issue Processors
(2015-07-01)
Wu, I-Wei
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Shann, Jean Jyh-Jiun
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Chung, Chung-Ping
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資訊工程學系
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Department of Computer Science
Next-generation digital entertainment and mobile communication devices are anticipated to require greater processor performance. To meet these demands, several researchers have attached a reconfigurable hardware accelerator to the base processor core. The reconfigurable hardware accelerator, termed a reconfigurable customized functional unit (RCFU), is usually realized by multiple processing elements (PE) organized in matrix form. The structure of the RCFU is generated from hot operation patterns of specific applications. Other than the RCFU, \'multiple-issue\' is another microarchitectural technique to increase the performance. However, the impact of combining both of these approaches in the same design is not yet well understood. This problem motivates us to design RCFU generation and exploitation algorithms for a multiple-issue processor. To allow more operations to execute on the RCFU simultaneously, the proposed generation algorithm merges several data-independent operation patterns to construct the RCFU architecture. To schedule operations on both the RCFU and functional units (FU) of the base processor core simultaneously, the proposed exploitation algorithm presents a model to represent all available computing resources from both the FUs of the base processor and the PEs in the RCFU. Using this model, the RCFU exploitation problem can be considered as an instruction-scheduling problem. Our experiment achieves an average improvement in execution performance of 50% compared with previous efforts [2, 5].