Browsing by Author "Wu, Jau-Yet"

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A Long Block Length BCH Decoder for DVB-S2 Application
(2009)
Lin, Yi-Min
;
Wu, Jau-Yet
;
Lin, Chien-Ching
;
Chang, Hsie-Chia
;
電子工程學系及電子研究所
In this paper, a low-complexity and full-mode BCH decoder with long block length for DVB-S2 application is presented. With the reversed error locator polynomial, our proposed reversed Berlekamp-Massey algorithm features a sharing architecture to perform parallel-4 syndrome and Chien search calculations. Concatenated with the LDPC decoder, which has a long decoding latency and a short period of data output time, the proposed parallel-4 BCH decoder ensures the sufficient throughput with only one bank memory. Moreover, a composite field divider instead of a large Galois field inversion table is also presented to reduce complexity. After implemented in 0.13 mu m CMOS technology, our parallel-4 BCH decoder occupied 44K gate count can reach 380Mb/s according to the post-layout simulations.
METHOD AND APPARATUS FOR DECODING SHORTENED BCH CODES OR REED-SOLOMON CODES
(2009-10-15)
CHANG, Hsie-Chia
;
Wu, Jau-Yet
;
Liao, Yen-Chin
The present invention proposes a method and apparatus for decoding BCH codes and Reed-Solomon codes, in which a modified Berlekamp-Massey algorithm is used to perform the decoding process and the efficiency of the decoder can be improved by re-defining the error locating polynomial as a reverse error locating polynomial, while the operation of the decoding process can be further realized by a common re-configurable module. Furthermore, the architecture of the decoder is consisted of a plurality of sets of re-configurable modules in order to provide parallel operations with different degrees of parallel so that the decoding speed requirement of the decoder in different applications can be satisfied.