Browsing by Author "Wu, Jieh-Tsorng"

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A 1 V 175 mu W 94.6 dB SNDR 25 kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques
(2018-01-01)
Liao, Sheng-Hui
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 2-1 MASH switched-capacitor delta-sigma modulator was fabricated using a 65 nm CMOS technology. We constantly alternate the circuit configurations of its internal integrators to optimize power consumption. The integrators are accelerated only when they are in crucial integration cycle. Operating at 5 MS/s sampling rate, this chip consumes 175 mu W from a 1 V supply. Assuming a 25 kHz signal bandwidth, it achieves 96.1 dB SNR, 94.6 dB SNDR, and 98.5 dB DR. Its active area is 1.13 x 0.34 mm(2).
A 1-V 100-dB Dynamic Range 24.4-kHz Bandwidth Delta-Sigma Modulator
(2013)
Chang, Chia-Ling
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 2-1 MASH delta-sigma modulator (DSM) was fabricated using a 90nm CMOS technology. Operating at 6.25 MHz clock rate, this chip consumes 860 mu W under a 1 V supply. The over-sampling ratio is 128, and the signal-bandwidth is 24.4 kHz. This chip achieves a performance of 88 dB SNDR and 90 dB SNR. Its dynamic range is 100 dB. The chip area is 0.44 mm(2).
A 1-V 175-mu W 94.6-dB SNDR 25-kHz Bandwidth Delta-Sigma Modulator Using Segmented Integration Techniques
(2019-09-01)
Liao, Sheng-Hui
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 2-1 multistage noise-shaping (MASH) switched-capacitor (SC) delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. We developed two separate segmented integration techniques to implement the first two integrators in the DSM. The techniques use both an inverter (IVT)-based opamp and a source-coupled-pair (SCP)-based opamp to relay the charge integration operation. This increases performance while saving power. The first integrator also operates more slowly during output sampling to further reduce power consumption. Operating at a 5-MS/s sampling rate, this chip consumes 175 mu W from a 1-V supply. For a 25-kHz signal bandwidth, it achieves a 96.1-dB signal-to-noise ratio (SNR), a 94.6-dB signal-to-noise-plus-distortion ratio (SNDR) and a 98.5-dB dynamic range (DR). Its active area is 1.13 x 0.34 mm(2).
A 10-Bit 200-MS/s Digitally-Calibrated Pipelined ADC Using Switching Opamps
(2012)
Fang, Bing-Nan
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 10-bit 200-MS/ s pipelined ADC was fabricated using a 90 nm CMOS technology. Switching opamps are used to save power. They are designed for high speed and fast turnon time. Digital background calibration is used to correct the conversion error caused by the low dc gain of the opamps. The ADC consumes 26 mW from a 1.1 V supply. Its measured DNL and INL are + 0.98/-0.81 LSB and + 1.4/-1.5 LSB respectively. Its measured SNDR and SFDR are 55 dB and 67.2 dB respectively. The chip active area is 0.69 mm(2).
A 10-Bit 300-MS/s Pipelined ADC With Digital Calibration and Digital Bias Generation
(2013-03-01)
Fang, Bing-Nan
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 10-bit pipelined ADC was fabricated using a 65 nm CMOS technology. To reduce power consumption, switching opamps are used. These switching opamps are designed to have a short turn-on time. Digital background calibration is employed to correct the A/D conversion error caused by the low dc gain of the opamps. The biasing voltages in each opamp are automatically generated using digital circuits. This bias scheme can maintain the settling behavior of the opamp against process-voltage-temperature variations. At 300 MS/s sampling rate, the ADC consumes 26.6 mW from a 1 V supply. Its measured DNL and INL are +0.52/-0.4 LSB and +0.99/-1.65 LSB respectively. Its measured SNDR and SFDR are 55.4 dB and 67.2 dB respectively. The chip active area is 0.36 mm(2).
A 12-Bit 1.25-GS/s DAC in 90 nm CMOS With > 70 dB SFDR up to 500 MHz
(2011-12-01)
Tseng, Wei-Hsin
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Fan, Chi-Wei
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A current-steering digital-to-analog converter (DAC) was fabricated using a 90 nm CMOS technology. Its dynamic performance is enhanced by adopting a digital random return-to-zero (DRRZ) operation and a compact current cell design. The DRRZ also facilitates a current-cell background calibration technique that ensures the DAC static linearity. The measured differential nonlinearity (DNL) is 0.5 LSB and the integral nonlinearity (INL) is 1.2 LSB. At 1.25 GS/s sampling rate, the DAC achieves a spurious-free dynamic range (SFDR) better than 70 dB up to 500 MHz input frequency. The DAC occupies an active area of 1100 x 750 mu m(2). It consumes a total of 128 mW from a 1.2 V and a 2.5 V supply.
A 16-mW 8-Bit 1-GS/s Digital-Subranging ADC in 55-nm CMOS
(2015-03-01)
Chung, Yung-Hui
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Wu, Jieh-Tsorng
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電機工程學系
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Department of Electrical and Computer Engineering
This paper presents a digital-subranging (sub-R) analog-to-digital conversion (ADC) architecture to improve the operation speed of sub-R ADCs. Long latency between coarse and fine conversions will slow down the conventional sub-R ADCs. The proposed digital-sub-R uses digital circuits to implement the sub-R function and shorten this latency, thus benefits the CMOS scaling. Furthermore, the dynamic comparators are used to save more ADC power consumption. Their accuracy is improved by the proposed pseudodifferential offset calibration loop. The digital-sub-R also helps to reduce the dynamic offset of the fine comparators caused by the input common-mode variation. Fabricated using a 55-nm CMOS technology, the reported 8-bit 1-GS/s ADC consumes only 16 mW from a 1.2 V supply. Measured signal-to-noise ratio (SNR) and spurious free dynamic range (SFDR) are 46 and 55 dB, respectively. Measured effective number of bits (ENOB) is seven bits at 10-MHz input frequency. At Nyquist input, the ENOB performance of 6.3 bits is still maintained. Its figure-of-merit is 197-fJ/conversion-step.
A 81-dB Dynamic Range 16-MHz Bandwidth Delta Sigma Modulator Using Background Calibration
(2013-09-01)
Wu, Su-Hao
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A fourth-order discrete-time delta-sigma modulator (DSM) was fabricated using a 65-nm CMOS technology. It combines low-complexity circuits and digital calibrations to achieve high speed and high performance. The DSM is a cascade of two second-order loops. It has a sampling rate of 1.1 GHz and an input bandwidth of 16.67 MHz with an oversampling ratio of 33. It uses high-speed opamps with a dc gain of only 10. Two different types of digital calibrations are used. We first employ the integrator leakage calibration to correct the poles of the integrators. We then apply the noise leakage calibration to minimize the leaking quantization noise from the first loop. The noise leakage calibration also relaxes the component-matching requirements. Both calibrations can operate in the background without interrupting the normal DSM operation. The chip's measured signal-to-noise-and-distortion ratio and dynamic range are 74.32 and 81 dB, respectively. The chip consumes 94 mW from a 1-V supply. The active area is 0.33 x 0.58 mm(2).
A 95-dBA DR Digital Audio Class-D Amplifier Using a Calibrated Digital-to-Pulse Converter
(2017-05-01)
Chang, Chih-Min
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A digital class-D amplifier (CDA) converts an audio digital stream into sound directly and power-efficiently. It first encodes the pulse-code-modulated audio input into a digital pulse-width-modulated (PWM) signal. It needs a digital-to-pulse converter (DPC) to translate this digital PWM signal into a series of analog binary pulses accurately. We report a 5-3 segmented DPC that includes both a counter and a delay line for pulse width conversion. The timing skews along the delay line are detected using a zero-crossing detection scheme and corrected in the digital domain. This calibration can operate continuously in the background. A digital CDA prototype was fabricated using a 65-nm CMOS technology. It includes the aforementioned PWM modulator and DPC. It also integrated an open-loop switching driver to deliver the DPC's output to a speaker. This digital CDA consumes 875 mu W under a 1-V supply when the input is zero and no output power is transferred to the external load. It can deliver 13.3 mW to a 32 Omega resistive load in the H-bridge topology with 89% power efficiency. For a 1-kHz sine-wave input, it achieves 95 dBA dynamic range, 93.6 dBA peak SNR, 86.4 dBA peak SNDR, and 0.006% THD at -2-dBFS input level. The core area of the chip is 0.87 x 0.5 mm(2).
A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration
(2007-10-01)
Lee, Zwei-Mei
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Wang, Cheng-Yeh
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mu m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. This ADC incorporates a single sample-and-hold amplifier which employs a precharged circuit configuration to mitigate performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each A/D channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 x 4.3 mm(2) and dissipates 909 mW from a 1.8 V supply.
A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background. calibration
(2006)
Lee, Zwei-Mei
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Wang, Cheng-Yeh
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Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 15-bit 125-MS/s two-channel time-interleaved pipelined ADC is fabricated in a 0.18 mu m CMOS technology, and achieves 91.9 dB SFDR, 69.9 dB SNDR for a 9.99 MHz input. The ADC uses a single sample-and-hold amplifier which employs a precharging circuit technique to mitigate the performance requirements for its opamp. Digital background calibration is applied to maintain the conversion linearity of each AID channel and also correct both gain and offset mismatches between the two channels. Excluding I/O buffers, the chip occupies an area of 4.3 x 4.3 mm(2) and dissipates 909 mW from a 1.8 V supply.
A CMOS 5.37-mW 10-Bit 200-MS/s Dual-Path Pipelined ADC
(2012-12-01)
Chai, Yun
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A 10-bit 200-MS/s pipelined ADC was fabricated using a standard 65 nm CMOS technology. We propose a dual-path amplification technique for residue generation. We split the pipeline stage into a coarse-stage multiplying digital-to-analog converter (MDAC) and a fine-stage MDAC. The opamps for these two MDACs require different specifications. They can be designed and optimized separately. They are turned off when not in use to save power. We modify the operation of a pipeline stage to accommodate the dual-path scheme by using time-interleaving capacitor sets. Operating at 200 MS/s sampling rate, this ADC consumes 5.37 mW from a 1 V supply. It achieves a signal-to-noise-plus-distortion ratio (SNDR) better than 55 dB SNDR over the entire Nyquist band. The chip active area is 0.19 mm(2).
A CMOS 6-Bit 16-GS/s Time-Interleaved ADC Using Digital Background Calibration Techniques
(2011-04-01)
Huang, Chun-Cheng
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Wang, Chung-Yi
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An 8-channel 6-bit 16-GS/s time-interleaved analog-to-digital converter (TI ADC) was fabricated using a 65 nm CMOS technology. Each analog-to-digital channel is a 6-bit flash ADC. Its comparators are latches without the preamplifiers. The input-referred offsets of the latches are reduced by digital offset calibration. The TI ADC includes a multi-phase clock generator that uses a delay-locked loop to generate 8 sampling clocks from a reference clock of the same frequency. The uniformity of the sampling intervals is ensured by digital timing-skew calibration. Both the offset calibration and the timing-skew calibration run continuously in the background. At 16 GS/s sampling rate, this ADC chip achieves a signal-to-distortion-plus-noise ratio (SNDR) of 30.8 dB. The chip consumes 435 mW from a 1.5 V supply. The ADC active area is 0.93 x 1.58 mm(2).
A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration
(2010)
Huang, Chun-Cheng
;
Wang, Chung-Yi
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Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An 8-channel 6-bit 16-GS/s time-interleaved ADC was fabricated using a 65nm CMOS technology. Each A/D channel is a flash ADC using latch-type comparator with background offset calibration. Timing skews among the channels are also continuously calibrated in the background. The chip achieves 42.3dB SFDR and 30.8dB SNDR at 16 GS/s sampling rate.
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
(2009)
Chung, Yung-Hui
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Wu, Jieh-Tsorng
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交大名義發表
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National Chiao Tung University
a 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power dissipation, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The linearity of the residue amplifier is enhanced by digital background calibration. The resolution of the comparators is improved by analog offset calibration. The ADC consumes 6mW from a 1V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34b. The FOM is 100 fJ per conversion-step.
A CMOS 6-mW 10-bit 100-MS/s Two-Step ADC
(2010-11-01)
Chung, Yung-Hui
;
Wu, Jieh-Tsorng
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 10-bit 100-MS/s two-step ADC was fabricated using a 90 nm CMOS technology. To reduce power consumption, the ADC uses latch-type comparators for signal digitalization and an open-loop amplifier for residue amplification. The accuracy of the comparators is improved by offset calibration. The gain accuracy and the linearity of the residue amplifier are enhanced by digital background calibration. The ADC consumes 6 mW from a 1 V supply. Measured SNR and SFDR are 58.2 dB and 75 dB respectively. Measured ENOB is 9.34 bits. The FOM is 100 fJ . V per conversion-step.
A CMOS 8-Bit 1.6-GS/s DAC With Digital Random Return-to-Zero
(2011-01-01)
Tseng, Wei-Hsin
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Wu, Jieh-Tsorng
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Chu, Yung-Cheng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A digital random return-to-zero technique is presented to improve the dynamic performance of current-steering digital-to-analog converters (DACs). To demonstrate the proposed technique, a CMOS 8-bit 1.6-GS/s DAC was fabricated in a 90-nm CMOS technology. The DAC achieves a spurious-free dynamic range better than 60 dB for a sine-wave input up to 460 MHz and better than 55 dB up to 800 MHz. The DAC consumes 90 mW of power.
A Computationally-Efficient PWM Technique for Digital Class-D Amplifiers
(2016)
Chang, Chih-Min
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
We describe a technique that digitally converts a pulse-code-modulated (PCM) signal to a pulse-width-modulation (PWM) signal. This technique is based on the naturally sampled PWM emulation scheme. Its computation is simplified by using empirical models. It provides sufficient accuracy with minimal computation. At 384 kHz sampling rate, the proposed technique can convert a sine wave to a PWM signal and achieve better than 92 dB total harmonic distortion (THD) for a sine wave frequency up to 20 kHz and a sine wave amplitude up to 90% of the full range.
A Multiphase Timing-Skew Calibration Technique Using Zero-Crossing Detection
(2009-06-01)
Wang, Chung-Yi
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes a timing-skew calibration technique which equalizes the phase spacings among multiphase clocks. The scheme uses simple sample-and-hold circuits controlled by the multiphase clocks to sample a common reference input. Phase spacing is measured by counting the number of zero crossings between two adjacent sampling sequences. A zero-crossing detection scheme is proposed. It has better immunity against the offsets of the comparators used in the detector. A digital calibration processor is also proposed. It examines the outputs from the zero-crossing detectors, and then adjusts the delays of clock buffers in order to minimize timing skews. The proposed calibration scheme does not demand stringent requirement for the reference input. Its application to a eight-channel 6-b time-interleaved analog-to-digital converter is demonstrated.
A robust and fast digital background calibration technique for pipelined ADCs
(2007-06-01)
Fan, Jen-Lin
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Wang, Chung-Yi
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Wu, Jieh-Tsorng
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
This paper presents a background calibration scheme for pipelined analog-to-digital converters (ADCs) that is robust and has short calibration time. For a switched-capacitor (SC) pipeline stage, by splitting its input sampling capacitor, a random sequence can be injected into the ADC's signal path, and then calibration data can be extracted from the ADC's digital output without interrupting its normal conversion operation. Using an input-dependent scheme to generate the calibration random sequence, no additional signal range is required to accommodate the extra calibration signal. Furthermore, using random choppers to scramble signal can ensure that all necessary calibration data can be collected within a given time regardless of input conditions, resulting in a more robust ADC. A split-channel ADC architecture is proposed to reduce the calibration time. The split-channel ADC consists of two A/D channels that receive the same analog input but employ different random sequences for calibration. The calibration time can be greatly reduced by comparing the digital outputs from both channels and then removing the embedded perturbations before extracting the calibration data. The proposed calibration techniques are analyzed by using both theoretical formulation and system-level simulation.