Browsing by Author "Wu, Kai-Chiang"

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Aging-aware Chip Health Prediction Adopting an Innovative Monitoring Strategy
(2019-01-01)
Wang, Yun-Ting
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Wu, Kai-Chiang
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Chou, Chung-Han
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Chang, Shih-Chieh
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資訊工程學系
Concerns exist that the reliability of chips is worsening because of downscaling technology. Among various reliability challenges, device aging is a dominant concern because it degrades circuit performance over time. Traditionally, runtime monitoring approaches are proposed to estimate aging effects. However, such techniques tend to predict and monitor delay degradation status for circuit mitigation measures rather than the health condition of the chip. In this paper, we propose an aging-aware chip health prediction methodology that adapts to workload conditions and process, supply voltage, and temperature variations. Our prediction methodology adopts an innovative on-chip delay monitoring strategy by tracing representative aging-aware delay behavior. The delay behavior is then fed into a machine learning engine to predict the age of the tested chips. Experimental results indicate that our strategy can obtain 97.40% accuracy with 4.14% area overhead on average. To the authors' knowledge, this is the first method that accurately predicts current chip age and provides information regarding future chip health.
Analysis and Optimization of Variable-Latency Designs in the Presence of Timing Variability
(2017-01-01)
Tsai, Chang-Lin
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Cheng, Chao-Wei
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Huang, Ning-Chi
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Wu, Kai-Chiang
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資訊工程學系
Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Required for dealing with the impact of timing variability better, detailed evaluation and analysis of circuit timing for VIM are actually not straightforward. In this paper, we present a systematic methodology for analyzing a VLD circuit, and identifying critical 1-cycle and 2-cycle paths/gates. Based on the criticality analysis, a gate sizing framework using particle swarm optimization (PSO) is proposed. Our objective is, in a less pessimistic fashion, making constructed VLD circuits better (less vulnerable to timing variability). The proposed framework is experimentally verified to be runtime-efficient and able to provide promising results. On average, an extra timing margin of 11% can be obtained without lengthening the clock period, and only 4% area overhead is introduced.
BTI-Aware Sleep Transistor Sizing Algorithm for Reliable Power Gating Designs
(2014-10-01)
Wu, Kai-Chiang
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Lin, Ing-Chao
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Wang, Yao-Te
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Yang, Shuen-Shiang
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資訊工程學系
Power gating is an effective way to reduce leakage power. This technique uses high V-th transistors, called sleep transistors, to turn off the power supply. However, sleep transistors suffer from the bias temperature instability (BTI) effect, resulting in an increased V-th, and reduced reliability. This paper proposes two BTI-aware sleep transistor sizing algorithms to reduce the total width of sleep transistors based on the distributed sleep transistor network structure. The proposed algorithms reduce total width by more than 16.08%. More area can be reduced if the BTI effect on both sleep and cluster transistors is considered.
Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency Designs
(2019-01-01)
Huang, Ning-Chi
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Chen, Yu-Guang
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Wu, Kai-Chiang
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資訊工程學系
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Department of Computer Science
Circuit performance has been the key design constraint for over a decade. Variable-latency design (VLD) paradigm was proposed for optimizing the overall performance in terms of throughput. In addition, process variations and aging effects manifest themselves as gate delay shifts, and in turn cause variability of circuit timing (timing variability). Besides, Power consumption is another important design consideration. To deal with the impact of timing variability and power issue better, in this paper, we present a VDD assignment framework based on genetic algorithm (GA) to minimize the power consumption of VLD. Our objective is making constructed VLD circuits more power-efficient under given tolerance to timing variability. Experimental results show that on average our methodology can achieve 24% dynamic power reduction, while preserving at least 8% timing margin, with only 5% overhead in circuit area and leakage power.
Fast WAT Test Structure for Measuring Vt Variance Based on Latch-based Comparators
(2017-01-01)
Lee, Kao-Chi
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Wu, Kai-Chiang
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Tsai, Chih-Ying
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Chao, Mango Chia-Tso
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資訊工程學系
As the technology of IC manufacturing continually scales down, process variations become more and more crucial than before. To statistically characterize local process variations, the traditional array-based test structure measures threshold voltage (Vt) for a sufficiently large number of devices-undertest (DUTs). However, the array-based test structure requires long time for DUT-by-DUT measurement; furthermore, it suffers from significant IR drop or leakage current due to the large number of DUTs, which results in the loss of measurement accuracy. In this paper, we present a novel sense-amplifierbased test structure that can monitor process variations based on rapid characterization of Vt variance, with marginal error of accuracy. A test-chip containing 120 NMOS and 120 PMOS DUTs has been implemented in 28nm CMOS process technology. Various experiments reveal promising efficiency and accuracy of the proposed test structure, for characterizing Vt variance.
ICE-RADAR: In-situ, Cost-Effective Razor Flip-Flop Deployment for Aging Resilience
(2019-01-01)
Wu, Kai-Chiang
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Huang, Wei-Tao
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Huang, Chiao-Yang
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資訊工程學系
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Department of Computer Science
Device aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nanoscale designs. In this paper, we propose to exploit timing speculation for aging resilience, based on deploying Razor flip-flops. By formulating the problem based on Boolean satisfiability, we can determine the optimal deployment of Razor flip-flops, such that maximum degree of aging resilience can be achieved in a cost-effective manner. Experimental results show that more than 50% of aging-induced performance degradation can be recovered, while reducing the number of required Razor flip-flops by more than 3X, as compared to the case of naive Razor flip-flop deployment.
Layout-Based Dual-Cell-Aware Tests
(2019-01-01)
Wu, Tse-Wei
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Lee, Dong-Zhen
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Wu, Kai-Chiang
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Huang, Yu-Hao
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Chen, Ying-Yen
Conventional fault models define their faulty behavior at the IO ports of standard cells with simple rules of fault activation and fault propagation. However, there still exist some defects inside a cell (intra-cell) or between two cells (dual-cell) that cannot be effectively detected by the test patterns of conventional fault models and hence become a source of DPPM. In order to further increase the defect coverage, many research works have been conducted to study the fault models resulting from different types of intra-cell and dual-cell defects, by SPICE-simulating each targeted defect with its equivalent circuit-level defect model. However, it was considered computationally infeasible to simulate every possible defective scenario for a cell library and obtain a complete set of cell-level fault models. In this paper, we present a new dual-cell-aware (DCA) framework based on examining the layout of two adjacent cells (i.e., a dual cell) to identify potential defects, where time-consuming RC extraction can be avoided and the runtime for SPICE simulation can be reduced. Experimental results and silicon data on a SoC product show that the proposed DCA framework can not only save runtime significantly but also maintain the promising efficacy of DCA tests for the objective of lowering DPPM.
Lifetime Reliability Trojan based on Exploring Malicious Aging
(2018-01-01)
Tseng, Tien-Hung
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Li, Shou-Chun
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Wu, Kai-Chiang
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資訊工程學系
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Department of Computer Science
Due to escalating complexity of hardware design and manufacturing, integrated circuits (ICs) are designed and fabricated in multiple nations, so are software tools. It makes hardware security become more subject to various kinds of tampering in the supply chain. Hardware Trojan horses (HTHs) can be implanted to facilitate the leakage of confidential information or cause the failure of a system. Reliability Trojan is one of the main categories of HTH attacks because its behavior is progressive and thus hard to be detected, or not considered malicious. In this work, we propose to insert reliability Trojan into a circuit which can finely control the circuit lifetime as specified by attackers (or even designers), based on manipulating BTI-induced aging behavior in a statistical manner, with the consideration of process variations (PVs). Experimental results show that, given a specified lifetime target and under the influence of PVs, the circuit is highly likely to fail within a desired lifetime interval, at the cost of little area overhead.
MAUI: Making Aging Useful, Intentionally
(2018-01-01)
Wu, Kai-Chiang
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Tseng, Tien-Hung
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Li, Shou-Chun
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資訊工程學系
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Department of Computer Science
Device aging, which causes significant loss on circuit performance and lifetime, has been a primary factor in reliability degradation of nanoscale designs. In this paper, we propose to take advantage of aging-induced clock skews (i.e., make them useful for aging tolerance) by manipulating these lime-varying skews to compensate for the performance degradation of logic networks. The goal is to assign achievable/reasonable aging-induced clock skews in a circuit, such that its overall performance degradation due to aging can be minimized, that is, the lifespan can be maximized. On average, 25% aging tolerance can be achieved with insignificant design overhead.
Methodology of Generating Timing-Slack-Based Cell-Aware Tests
(2019-01-01)
Nien, Yu-Teng
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Wu, Kai-Chiang
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Lee, Dong-Zhen
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Chen, Ying-Yen
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Chen, Po-Lin
In order to reduce DPPM (defect parts per million), cell-aware (CA) methodology was proposed to cover various types of intra-cell defects. The resulting CA faults can be a 1-time-frame (ltf) or 2-time-frame (2tf) fault, and 2tf CA tests were experimentally verified to be capable of catching a significant number of defective parts not covered by other conventional tests. In this paper, we present a novel methodology for generating 2tf CA tests based on timing slack analysis. The proposed 2tf CA fault model, aware of timing slack and named TS, defines a fault (i) on a cell instance basis, and (ii) based on per-instance timing criticality (according to timing slack). More explicitly, for each cell instance with a specific defect injected, we check its output capacitive load and derive the corresponding extra delay. By comparing the extra delay against timing slack of the cell instance, a delay fault can be defined, and according to its severity, the fault can be further classified into small-delay fault or gross-delay fault. In contrast to prior 2tf CA methodology that is on a cell (rather than cell instance) basis and unaware of timing criticality/slack, our methodology can identify "more realistic" faults which really need to be considered, and potentially the cost/effort for testing those 2tf CA faults can be reduced. Experimental results on a set of 28nm industrial designs demonstrate that, due to more realistic fault identification, the numbers of identified small-delay faults and corresponding test patterns to be applied can be reduced by 35.1% and 24.1% respectively, leading to 40.7% reduction in the runtime of ATPG.
Sensor-Based Approximate Adder Design for Accelerating Error-Tolerant and Deep-Learning Applications
(2019-01-01)
Huang, Ning-Chi
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Chen, Szu-Ying
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Wu, Kai-Chiang
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資訊工程學系
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Department of Computer Science
Approximate computing is an emerging strategy which trades computational accuracy for computational cost in terms of performance, energy, and/or area. In this paper, we propose a novel sensor-based approximate adder for high-performance energy-efficient arithmetic computation, while considering the accuracy requirement of error-tolerant applications. This is the first work using in-situ sensors for approximate adder design, based on monitoring online transition activity on the carry chain and speculating on carry propagation/truncation. On top of a fully-optimized ripple-carry adder, the performance of our adder is enhanced by 2.17X. When applied in error-tolerant applications such as image processing and handwritten digit recognition, our approximate adder leads to very promising quality of results compared to the case when an accurate adder is used.
Sensor-Based Time Speculation in the Presence of Timing Variability
(2018-06-01)
Chou, Chung-Han
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Chang, Tsui-Yun
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Wu, Kai-Chiang
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Chang, Shih-Chieh
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資訊工程學系
Time speculation has been widely used to achieve high performance in modern design as it exploits average-case timing optimization instead of worst-case timing optimization focusing on reducing longest path delay which rarely happens. Variable-latency design (VLD) style is one research category of time speculation. Since process and environmental variations are hard to predict, traditional variable-latency units (VLUs) designed at presilicon stage will suffer significant performance loss due to pessimistic assumptions for addressing variations. In this paper, we propose a novel sensor-based, transition-aware VLU (S-VLU) scheme adapting to process-voltage-temperature (PVT) variations by using in situ sensors to obtain real-time transition information in a circuit. Moreover, we also propose a sensor deployment strategy to achieve near-maximal performance gain. On average, the S-VLU achieves a 31.27% performance improvement as compared to a 19.26% improvement by using traditional HL. The area overhead of the S-VLU is 13.48%. To the best of the authors' knowledge, this is the first wok to address PVT variations in VLD style.
Workload-Aware Lifetime Trojan based on Statistical Aging Manipulation
(2017-01-01)
Tseng, Tien-Hung
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Wang, Shu-Sheng
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Chen, Jian-You
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Wu, Kai-Chiang
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資訊工程學系
Due to escalating complexity of hardware design and manufacturing, not only are integrated circuits (ICs) designed and fabricated in multiple nations, but also software tools may be supplied worldwide. It makes hardware security become more subject to various kinds of tampering in the supply chain. Hardware Trojan horses (HTHs) can be implanted to facilitate the leakage of confidential information or cause the failure of a system. Reliability Trojan is one of the main categories of HTH attacks because its behavior is progressive and is thus not trivial to be detected, or not considered malicious. In this work, we propose to insert reliability Trojan into a circuit which can finely controls the circuit lifetime as specified by attackers (or even designers), based on manipulating BTI-induced aging behavior in a statistical manner. Experimental results show that, given a specified lifetime target, the resulting lifetime can mostly be bounded within 90% similar to 110% of the target. Instead, in a typical design considering pessimistic corners, the resulting lifetime is usually far longer than the target.