Browsing by Author "Wu, Kun-Long"

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77-110 GHz 65-nm CMOS Power Amplifier Design
(2014-05-01)
Wu, Kun-Long
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Lai, Kuan-Ting
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Hu, Robert
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Jou, Christina F.
;
Niu, Dow-Chih
This paper details the development of our millimeter-wave wideband power amplifier design. By treating the power combiner as an impedance transformer which allows different loading impedance to be taken into account, a compact wideband power-combining network can be constructed. With small transmission-line attenuation being sustained and maximum output power easily extracted from the transistors over the 77-110 GHz frequency range, a power amplifier can then be designed using 65-nm CMOS process to cover the whole W-band. In the on-wafer measurement, the gain is around 18 dB, the output reflection coefficients is below -10 dB, and the output-referred 1 dB compression point can reach 12 dBm at 1.2 V bias condition; when the bias is increased to 2.5 V, a 18 dBm output power is recorded. To our knowledge, this is the first CMOS power amplifier that covers the whole W-band.
77GHz Power Amplifier Design Using WIN 0.1 mu m GaAs pHEMT Process
(2014-01-01)
Lai, Kuan-Ting
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Wu, Kun-Long
;
Hu, Robert
;
Jou, Christina F.
;
交大名義發表
This paper reports our 77GHz power-amplifier designs using WIN 0.1 mu m GaAs pHEMT process provided by the commercial WIN foundry. The first two stages of the power amplifier is made of common-source transistors for gain amplification, and then followed by two-and four-paralleled transistors where the 3dB two-way Wilkinson power splitters/combiners for large output power delivery are used. All the by-pass capacitors for drain and gate biases have been optimized to have small series impedance at W-band. The input DC-blocking capacitor is made coupled lines, which also functions as tuning circuit. With 2.5V and 350mA drain bias, the small-signal gain is 12dB, as measured on-wafer at room temperature; the output-referred 1dB compression point is 6dBm. With 3dBm input power, the saturated output power is around 8.6dBm. Good input- and output-port matching has also been observed. The chip size is 1000x2500 mu m(2) and it consumes 875mW.
A 34-42GHz Single-Side-Band Transmitter with Switchable VCO/PLL in 90nm-CMOS Process
(2017-01-01)
Huang, Ching-Ying
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Wu, Kun-Long
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Hu, Robert
;
Chang, Chi-Yang
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電子工程學系及電子研究所
This manuscript describes a 34-42GHz single-sideband 90nm-CMOS transmitter where PLL has been integrated into the LO chain and, with I/Q input and two-stage up-conversion, a 30dB image-rejection ratio is achieved within the intended bandwidth. This transmitter's wideband tuning range is made possible by the use of additional capacitor on the VCO, and the phase noise of the resulting RF output is in the range of -70 to -90dBc/Hz at 1MHz, and all below 100dBc/Hz at 10MHz. The circuit's IF-to-RF conversion gain is 30dB, with saturated output power around 5dBm, and the total power consumption is 260mW. Through the control of the power amplifier's drain bias, a 50dB power level difference can be obtained, thus allows signal modulation and further combination with the receiver. This 1100x650um(2) transmitter can be used as a prototypical circuit to explore next-generation mobile communication and civilian radar array systems.
Analysis of wide-IF-band 65 nm-CMOS mixer for 77-110 GHz radio-astronomical receiver design
(2019-05-01)
Huang, Ching-Ying
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Wu, Kun-Long
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Hu, Robert
;
Chang, Chi-Yang
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電子工程學系及電子研究所
This manuscript presents the design of a W-band receiver in which an radio frequency-low noise amplifier (RF-LNA), a wideband mixer, intermediate frequency (IF) amplification, a local oscillator frequency (LO) tripler and a driving amplifier are all integrated into one single chip of 1050 x 820 mu m(2). To effectively extend the mixer's IF bandwidth while retaining its conversion gain, impacts of the mixing transistor's drain bias and output loading impedance are explored using a dual-modulation conversion-matrix method, which allows both the LO-induced transconductance modulation and channel-conductance modulation to be considered simultaneously. It is shown that, by merging the input capacitance of the IF amplifier into a high-impedance artificial transmission line, an actively biased mixer can have constant conversion gain over broad bandwidth. A 77-110 GHz 65 nm-complementary metal-oxide-semiconductor (CMOS) receiver with 33 GHz IF bandwidth is then designed and measured. Its conversion gain and noise figure are 10 and 20 dB, respectively, and the input-referred P1 dB is -15 dBm; the overall power consumption is 330 mW under 1.3 V drain bias.
DC-50GHz Wideband Phase-Compensated 90nm-CMOS Active Balun Design
(2015)
Wu, Kun-Long
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Lai, Kuan-Ting
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Hu, Robert
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Chang, Chi-Yang
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電機學院
This manuscript explores the output phase imbalance observed in the common-gate common-source transistors, and gives a mathematical formulation in determining the length of the compensation transmission line. To demonstrate the validity of this wideband phase-compensation technique, a DC-50GHz active balun is designed using commercial 90nm-CMOS process and then measured, where the phase imbalance is less than 5 degrees while the magnitude imbalance is within 1dB. All ports are well-matched and positive gain has been sustained up to 50GHz; the output-referred 1dB compression point is around 3dBm. With 3V and 32.5mA drain bias, the total power consumption is 97.5mW. To our knowledge, this is the widest active balun ever designed with such tight output phase requirement.
IL analysis for 8-way power combining network in 77-110 GHz 40 nm-complementary metal-oxide-semiconductor PA design
(2019-11-01)
Huang, Ching-Ying
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Wu, Pin-Hsuan
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Wu, Kun-Long
;
Hu, Robert
;
Chang, Chi-Yang
In this study, the authors will investigate the insertion loss (IL) of the broadband 8-way power combiner used in their millimetre-wave power amplifier (PA) design. By treating this combiner as impedance transformer under resistor-capacitor (RC)-loading condition, both the characteristic impedance and electrical length of the constituting metal lines can be obtained, where the much shorter line length suggests wider bandwidth and lower IL. However, proper loss analysis must take into account the multi-reflection of voltage wave along these mismatched transmission lines, i.e. the use of the power attenuation expression ${\rm e}<^>{ - 2\alpha L}$e-2 alpha L is just not accurate enough. With their derived equations, it shows that the IL of their proposed 8-way combiner can be as low as 0.92 dB at 94 GHz, which is much smaller than the 1.5 dB for the conventional quarter-wavelength combiner. Mathematics for the IL of the drain-bias shunt stub and the output DC-blocking capacitor has also been derived. As a demonstration, a 77-110 GHz 40 nm-complementary metal-oxide-semiconductor PA made of cascode transistors is then designed that has more than 18 dB gain, and its OP1 dB is around 13 dBm across the whole frequency range.
Microwave and Millimeter-Wave CMOS Frequency Doubler and Tripler Designs
(2014-01-01)
Wu, Kun-Long
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Tsai, Han-Ting
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Tseng, Pei-Ling
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Hu, Robert
;
Jou, Christina F.
This manuscript describes our 17.4GHz 0.18 mu m-CMOS doubler and 77GHz 65nm-CMOS tripler designs. For the doubler, attention has been made on effectively suppressing the fundamental, third and forth harmonics using LLC filtering networks and balun. As for the tripler, the unwanted second-order harmonic can be suppressed through the use of large source impedance on the differential pair while the fundamental signal leakage is removed by an embedded notch filter; therefore, the intended third-harmonic output is almost 40dB larger than all the other spurious signals. The tripler chip size is 700x940um, and it consumes 93mW under 1.2V bias; the 3dB bandwidth for output is 9GHz.
Microwave and Millimeter-Wave Cryogenic Wideband LNA Design and Characterization
(2015)
Chen, Ying
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Li, Zheng-Kai
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Wu, Kun-Long
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Li, Bin
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Hu, Robert
-This manuscript reports our progress in designing wideband LNAs for use in radio-astronomical receivers. These include two WIN-150nm and five WIN-100nm GaAs pHEMT LNAs. Following a general description of design methodology, the LNAs\' simulated and measured results at room temperature will be presented. To make these LNAs eligible for low temperature applications, a cryogenic noise measurement system using multi-point variable-temperature-load (VTL) method is constructed where the system is computer controlled, and both the noise calibration and de-embedding concerns are properly addressed. At 14K ambient temperature, the 5-10GHz LNA has its averaged T. equal to 8K and the 8-20GHz LNA has its T. around 10K
OMMIC 70nm-mHEMT LNA Design
(2017-01-01)
Chen, Ying
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Wu, Kun-Long
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Huang, Ching-Ying
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Chang, Che-Kun
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Sun, Xin
This paper describes our progress in the design of cryogenic LNAs using OMMIC 70nm mHEMT for the Square Kilometer-Array (SKA) project and the Shanghai 65-Meter radio astronomical telescope. Different LNAs covering the aggregate 1 similar to 40GHz frequency range are designed and measured on-wafer at room temperature, and T-n for the 1 similar to 10, 5 similar to 15, and 10 similar to 40GHz LNAs are 80K, 90K, and 120K, respectively, with the gain all larger than 20dB. One 1 similar to 10GHz LNA chip is then packaged and tested cryogenically, and the noise temperature improvement factor is 6 similar to 8, which is smaller than what can be obtained from the WIN pHEMT. Performance repeatability among different chips has been carried out.