Browsing by Author "Wu, Ming-Hua"

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POSA: Power-State-Aware Buffered Tree Construction
(2009)
Jiang, Iris Hui-Ru
;
Wu, Ming-Hua
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Buffering without considering power states in multiple supply voltage designs may result in infeasible signals. POSA is the first work to handle this issue. Our buffered tree guarantees feasibility all the times, even when some parts of the design shut down. This feature is one of the key techniques to fulfill power-aware design methodology.
Power-State-Aware Buffered Tree Construction
(2008)
Jiang, Iris Hui-Ru
;
Wu, Ming-Hua
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Interconnect delay and low power are two of the main issues in nano technology. Buffer insertion during routing effectively reduces interconnect delay; power state management and multiple supply voltage significantly lower power consumption. However, buffering without considering power states in multiple supply voltage designs may cause the signal integrity problem. This paper first considers power states into buffered tree construction. Based on a hierarchical approach combined with dynamic programming, we can simultaneously minimize power, satisfy timing constraints and maintain signal integrity.